LTC2268-12/
LTC2267-12/LTC2266-12
12-Bit, 125Msps/105Msps/
80Msps Low Power Dual ADCs
FEATURES
DESCRIPTION
TheLTC®2268-12/LTC2267-12/LTC2266-12are2-channel,
simultaneous sampling 12-bit A/D converters designed
for digitizing high frequency, wide dynamic range signals.
They are perfect for demanding communications applica-
tions with AC performance that includes 70.6dB SNR and
88dB spurious free dynamic range (SFDR). Ultralow jitter
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2-Channel Simultaneous Sampling ADC
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70.6dB SNR
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88dB SFDR
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Low Power: 292mW/2ꢀ8mW/200mW Total,
146mW/119mW/100mW per Channel
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Single 1.8V Supply
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Serial LVDS Outputs: 1 or 2 Bits per Channel
of0.15ps
allowsundersamplingofIFfrequencieswith
RMS
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Selectable Input Ranges: 1V to 2V
excellent noise performance.
P-P
P-P
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800MHz Full Power Bandwidth S/H
DC specs include 0.ꢀLSB INL (typ), 0.1LSB DNL (typ)
and no missing codes over temperature. The transition
Shutdown and Nap Modes
Serial SPI Port for Configuration
noise is a low 0.ꢀLSB
.
RMS
Pin Compatible 14-Bit and 12-Bit Versions
The digital outputs are serial LVDS to minimize the num-
ber of data lines. Each channel outputs two bits at a time
(2-lane mode). At lower sampling rates there is a one bit
per channel option (1-lane mode). The LVDS drivers have
optional internal termination and adjustable output levels
to ensure clean signal integrity.
40-Pin (6mm × 6mm) QFN Package
APPLICATIONS
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Communications
Cellular Base Stations
Software Defined Radios
Portable Medical Imaging
Multichannel Data Acquisition
Nondestructive Testing
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–
The ENC and ENC inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL, or
CMOS inputs. An internal clock duty cycle stabilizer al-
lows high performance at full speed for a wide range of
clock duty cycles.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
LTC2268-12, 125Msps,
1.8V
V
1.8V
OV
2-Tone FFT, fIN = 70MHz and 75MHz
DD
DD
0
–10
–20
–30
–40
CH.1
ANALOG
INPUT
OUT1A
OUT1B
12-BIT
S/H
S/H
ADC CORE
SERIALIZED
DATA
SERIALIZER
OUT2A
OUT2B
CH.2
ANALOG
INPUT
–50
–60
–70
12-BIT
ADC CORE
LVDS
OUTPUTS
DATA
CLOCK
OUT
–80
–90
ENCODE
INPUT
PLL
FRAME
–100
–110
–120
GND
OGND
0
20
30
40
50
60
10
FREQUENCY (MHz)
226812 TA01
226812 TA01b
22687612f
1