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LTC2266IUJ-14#PBF PDF预览

LTC2266IUJ-14#PBF

更新时间: 2024-11-12 19:55:55
品牌 Logo 应用领域
凌特 - Linear 转换器
页数 文件大小 规格书
32页 731K
描述
LTC2266-14 - 14-Bit, 80Msps Low Power Dual ADCs; Package: QFN; Pins: 40; Temperature Range: -40°C to 85°C

LTC2266IUJ-14#PBF 技术参数

是否Rohs认证: 符合生命周期:Transferred
零件包装代码:QFN包装说明:HVQCCN, LCC40,.24SQ,20
针数:40Reach Compliance Code:compliant
ECCN代码:3A991.C.3HTS代码:8542.39.00.01
风险等级:3.67最大模拟输入电压:2 V
最小模拟输入电压:-2 V转换器类型:ADC, PROPRIETARY METHOD
JESD-30 代码:S-PQCC-N40JESD-609代码:e3
长度:6 mm最大线性误差 (EL):0.0168%
湿度敏感等级:1模拟输入通道数量:2
位数:14功能数量:1
端子数量:40最高工作温度:85 °C
最低工作温度:-40 °C输出位码:OFFSET BINARY, 2'S COMPLEMENT BINARY
输出格式:SERIAL封装主体材料:PLASTIC/EPOXY
封装代码:HVQCCN封装等效代码:LCC40,.24SQ,20
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260电源:1.8 V
认证状态:Not Qualified采样速率:80 MHz
采样并保持/跟踪并保持:SAMPLE座面最大高度:0.8 mm
子类别:Analog to Digital Converters标称供电电压:1.8 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:6 mmBase Number Matches:1

LTC2266IUJ-14#PBF 数据手册

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LTC2268-14/  
LTC2267-14/LTC2266-14  
14-Bit, 125Msps/105Msps/  
80Msps Low Power Dual ADCs  
FeaTures  
DescripTion  
TheLTC®2268-14/LTC2267-14/LTC2266-14are2-channel,  
simultaneous sampling 14-bit A/D converters designed  
for digitizing high frequency, wide dynamic range signals.  
They are perfect for demanding communications applica-  
tions with AC performance that includes 73.1dB SNR and  
88dB spurious free dynamic range (SFDR). Ultralow jitter  
n
2-Channel Simultaneous Sampling ADC  
n
73.1dB SNR  
n
88dB SFDR  
n
Low Power: 299mW/243mW/203mW Total  
n
150mW/121mW/101mW Per Channel  
n
Single 1.8V Supply  
n
Serial LVDS Outputs: 1 or 2 Bits Per Channel  
of0.15ps  
allowsundersamplingofIFfrequencieswith  
RMS  
n
Selectable Input Ranges: 1V to 2V  
excellent noise performance.  
P-P  
P-P  
n
n
n
n
n
800MHz Full Power Bandwidth S/H  
DC specs include ±1LSB INL (typ), ±0.3LSB DNL (typ)  
Shutdown and Nap Modes  
and no missing codes over temperature. The transition  
Serial SPI Port for Configuration  
noise is a low 1.2LSB  
.
RMS  
Pin Compatible 14-Bit and 12-Bit Versions  
The digital outputs are serial LVDS to minimize the num-  
ber of data lines. Each channel outputs two bits at a time  
(2-lane mode). At lower sampling rates there is a one bit  
per channel option (1-lane mode). The LVDS drivers have  
optional internal termination and adjustable output levels  
to ensure clean signal integrity.  
40-Pin (6mm × 6mm) QFN Package  
applicaTions  
n
Communications  
n
Cellular Base Stations  
n
Software Defined Radios  
+
The ENC and ENC inputs may be driven differentially  
or single-ended with a sine wave, PECL, LVDS, TTL, or  
CMOS inputs. An internal clock duty cycle stabilizer al-  
lows high performance at full speed for a wide range of  
clock duty cycles.  
n
Portable Medical Imaging  
n
Multichannel Data Acquisition  
n
Nondestructive Testing  
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear  
Technology Corporation. All other trademarks are the property of their respective owners.  
Typical applicaTion  
LTC2268-14, 125Msps,  
1.8V  
V
1.8V  
OV  
2-Tone FFT, fIN = 70MHz and 75MHz  
DD  
DD  
0
–10  
–20  
–30  
–40  
CH.1  
ANALOG  
INPUT  
OUT1A  
OUT1B  
14-BIT  
S/H  
S/H  
ADC CORE  
SERIALIZED  
DATA  
SERIALIZER  
OUT2A  
OUT2B  
CH.2  
ANALOG  
INPUT  
–50  
–60  
–70  
14-BIT  
ADC CORE  
LVDS  
OUTPUTS  
DATA  
CLOCK  
OUT  
–80  
–90  
ENCODE  
INPUT  
PLL  
FRAME  
–100  
–110  
–120  
GND  
OGND  
0
20  
30  
40  
50  
60  
10  
FREQUENCY (MHz)  
226814 TA01  
226814 TA01b  
22687614fa  
1

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