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LRS1331B PDF预览

LRS1331B

更新时间: 2024-11-06 13:09:31
品牌 Logo 应用领域
夏普 - SHARP 闪存静态存储器
页数 文件大小 规格书
26页 216K
描述
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LRS1331B 数据手册

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LRS1331  
Stacked Chip  
16M Flash Memory and 4M SRAM  
Data Sheet  
– Thirty-one 32K-word main blocks  
– Bottom boot location  
FEATURES  
• Flash Memory and SRAM  
– Extended cycling capability  
– 100,000 block erase cycles  
– Enhanced automated suspend options  
– Word write suspend to read  
– Block erase suspend to word write  
– Block erase suspend to read  
• Stacked Die Chip Scale Package  
• 72-ball 8 mm × 11 mm CSP plastic package  
• Power supply: 2.7 V to 3.6 V  
• Operating temperature: -25°C to +85°C  
• Flash Memory  
• SRAM  
– Access time (MAX.): 90 ns  
– Operating current (MAX.)  
(The current for F-VCC pin and F-VCCW pin):  
– Read: 25 mA (tCYCLE = 200 ns)  
– Word write: 57 mA  
– Access time (MAX.): 85 ns  
– Operating current: 45 mA (MAX.)  
– Standby current: 15 µA (MAX.)  
– Data retention current: 2 µA (MAX.)  
– Block erase: 42 mA  
– Standby current (the current for F-VCC pin): 15 µA  
(MAX. F-RP GND 0.2 V)  
– Optimized array blocking architecture  
DESCRIPTION  
The LRS1331 is a combination memory organized as  
1,048,576 × 16-bit flash memory and 262,144 × 16-bit  
static RAM in one package.  
– Two 4K-word boot blocks  
– Six 4K-word parameter blocks  
PIN CONFIGURATION  
72-BALL FBGA  
INDEX  
TOP VIEW  
1
2
3
4
5
6
7
8
9
10  
11  
12  
A
B
C
D
E
F
NC  
NC  
NC  
A11  
A15  
A14  
A13  
A12 F-GND NC  
NC  
NC  
A16  
A8  
A10  
T1  
A9 DQ15 S-WE DQ14 DQ7  
S-A17 DQ13 DQ6 DQ4 DQ5  
F-RY/  
BY  
F-WE  
GND F-RP T2  
T4  
DQ12 S-CE2 S-VCC F-VCC  
F-WP F-VPP F-A19 DQ11  
S-LB S-UB S-OE NC  
T3  
DQ9 DQ8 DQ0 DQ1  
A3 A2 A1 S-CE1  
DQ10 DQ2 DQ3  
G
H
F-A18 F-A17  
A7  
A4  
A6  
A0  
NC  
NC  
NC  
A5  
F-CE F-GND F-OE NC  
NC  
NC  
NOTE: All F-GND and S-GND pins are connected on the board.  
Two NC pins at the corner are connected.  
LRS1331-1  
Figure 1. LRS1331 Pin Configuration  
Data Sheet  
1

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