Datasheet > LQFP48

LQFP48

更新时间： 2024-11-05 12:46:35

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		闪存通信
页数	文件大小	规格书
79页	1115K
描述
Low-density access line, ARM-based 32-bit MCU with 16 or 32 KB Flash, 5 timers, ADC and 4 communication interfaces

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数据手册

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LQFP48 数据手册

STM32F101x4

STM32F101x6

Low-density access line, ARM-based 32-bit MCU with

16 or 32 KB Flash, 5 timers, ADC and 4 communication interfaces

Features

■ Core: ARM 32-bit Cortex™-M3 CPU

– 36 MHz maximum frequency,

1.25 DMIPS/MHz (Dhrystone 2.1)

LQFP64

10 x 10 mm

LQFP48

7 x 7 mm

VFQFPN48

7 × 7 mm

VFQFPN36

6 × 6 mm

performance at 0 wait state memory

access

– Single-cycle multiplication and hardware

division

■

Up to 5 timers

–

Up to two16-bit timers, each with up to 4

IC/OC/PWM or pulse counter

■ Memories

– 2 watchdog timers (Independent and

Window)

– 16 to 32 Kbytes of Flash memory

– 4 to 6 Kbytes of SRAM

– SysTick timer: 24-bit downcounter

■ Clock, reset and supply management

■ Up to 4 communication interfaces

– 2.0 to 3.6 V application supply and I/Os

– POR, PDR and programmable voltage

detector (PVD)

– 4-to-16 MHz crystal oscillator

– Internal 8 MHz factory-trimmed RC

– Internal 40 kHz RC

– 1 x I C interface (SMBus/PMBus)

– Up to 2 USARTs (ISO 7816 interface, LIN,

IrDA capability, modem control)

– 1 × SPI (18 Mbit/s)

■ CRC calculation unit, 96-bit unique ID

– PLL for CPU clock

– 32 kHz oscillator for RTC with calibration

■ ECOPACK packages

Table 1.

Device summary

Part number

STM32F101C4,

■ Low power

– Sleep, Stop and Standby modes

Reference

– V

supply for RTC and backup registers

BAT

STM32F101x4

STM32F101R4,

STM32F101T4

■ Debug mode

– Serial wire debug (SWD) and JTAG

interfaces

STM32F101C6,

STM32F101R6,

STM32F101T6

STM32F101x6

■ DMA

– 7-channel DMA controller

– Peripherals supported: timers, ADC, SPIs,

I Cs and USARTs

■ 1 × 12-bit, 1 µs A/D converter (up to 16

channels)

– Conversion range: 0 to 3.6 V

– Temperature sensor

■ Up to 51 fast I/O ports

– 26/37/51 I/Os, all mappable on 16 external

interrupt vectors and almost all 5 V-tolerant

April 2011

Doc ID 15058 Rev 5

1/79

www.st.com

12 3 4 5 6 7...79

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