Datasheet > LMK04000

LMK04000

更新时间： 2024-11-14 11:37:19

品牌	Logo	应用领域
美国国家半导体 - NSC		时钟
页数	文件大小	规格书
54页	1171K
描述
Low-Noise Clock Jitter Cleaner with Cascaded PLLs

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LMK04000 数据手册

September 10, 2010

LMK04000 Family

Low-Noise Clock Jitter Cleaner with Cascaded PLLs

1.0 General Description

2.0 Features

The LMK04000 family of precision clock conditioners pro-

vides low-noise jitter cleaning, clock multiplication and distri-

bution without the need for high-performance voltage con-

trolled crystal oscillators (VCXO) module. Using a cascaded

PLLatinum™ architecture combined with an external crystal

and varactor diode, the LMK04000 family provides sub-200

femtosecond (fs) root mean square (RMS) jitter performance.

Cascaded PLLatinum PLL Architecture

■

PLL1

—

Phase detector rate of up to 40 MHz

■

Integrated Low-Noise Crystal Oscillator Circuit

Dual redundant input reference clock with LOS

PLL2

—

Normalized [1 Hz] PLL noise floor of -224 dBc/Hz

■

The cascaded architecture consists of two high-performance

phase-locked loops (PLL), a low-noise crystal oscillator cir-

cuit, and a high-performance voltage controlled oscillator

(VCO). The first PLL (PLL1) provides a low-noise jitter cleaner

function while the second PLL (PLL2) performs the clock gen-

eration. PLL1 can be configured to either work with an exter-

nal VCXO module or use the integrated crystal oscillator with

an external crystal and a varactor diode. When used with a

very narrow loop bandwidth, PLL1 uses the superior close-in

phase noise (offsets below 50 kHz) of the VCXO module or

the crystal to clean the input clock. The output of PLL1 is used

as the clean input reference to PLL2 where it locks the inte-

grated VCO. The loop bandwidth of PLL2 can be optimized

to clean the far-out phase noise (offsets above 50 kHz) where

the integrated VCO outperforms the VCXO module or crystal

used in PLL1.

Phase detector rate up to 100 MHz

Input frequency-doubler

Integrated Low-Noise VCO

Ultra-Low RMS Jitter Performance

■

150 fs RMS jitter (12 kHz – 20 MHz)

200 fs RMS jitter (100 Hz – 20 MHz)

—

LVPECL/2VPECL, LVDS, and LVCMOS outputs

■

Support clock rates up to 1080 MHz

Default Clock Output (CLKout2) at power up

Five dedicated channel divider and delay blocks

Pin compatible family of clocking devices

Industrial Temperature Range: -40 to 85 °C

3.15 V to 3.45 V operation

The LMK04000 family features dual redundant inputs, five

differential outputs, and an optional default-clock upon power

up. The input block is equipped with loss of signal detection

and automatic or manual selection of the reference clock.

Each clock output consists of a programmable divider, a

phase synchronization circuit, a programmable delay, and an

LVDS, LVPECL, or LVCMOS output buffer. The default start-

up clock is available on CLKout2 and it can be used to provide

an initial clock for the field-programmable gate array (FPGA)

or microcontroller that programs the jitter cleaner during the

system power up sequence.

Package: 48 pin LLP (7.0 x 7.0 x 0.8 mm)

3.0 Target Applications

Data Converter Clocking

■

Wireless Infrastructure

Networking, SONET/SDH, DSLAM

Medical

Military / Aerospace

Test and Measurement

Video

30027140

PLLatinum™ is a trademark of National Semiconductor Corporation.

TRI-STATE^®is a registered trademark of National Semiconductor Corporation.

300271

www.national.com

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与LMK04000相关器件

型号	品牌	获取价格	描述	数据表
LMK04000BISQ	NSC	获取价格	Low-Noise Clock Jitter Cleaner with Cascaded PLLs
LMK04000BISQ/NOPB	TI	获取价格	具有级联 PLL 的精密时钟调节器低噪声时钟抖动消除器 \| RHS \| 48 \| -40
LMK04000BISQE	NSC	获取价格	Low-Noise Clock Jitter Cleaner with Cascaded PLLs
LMK04000BISQE/NOPB	TI	获取价格	具有级联 PLL 的精密时钟调节器低噪声时钟抖动消除器 \| RHS \| 48 \| -40
LMK04000BISQX	NSC	获取价格	Low-Noise Clock Jitter Cleaner with Cascaded PLLs
LMK04000BISQX/NOPB	TI	获取价格	具有级联 PLL 的精密时钟调节器低噪声时钟抖动消除器 \| RHS \| 48 \| -40
LMK04001	TI	获取价格	具有 1430MHz 至 1570MHz VCO 的低噪声抖动消除器：3 路输出用于 2V
LMK04001BISQ	NSC	获取价格	Low-Noise Clock Jitter Cleaner with Cascaded PLLs
LMK04001BISQ/NOPB	TI	获取价格	具有 1430MHz 至 1570MHz VCO 的低噪声抖动消除器：3 路输出用于 2V
LMK04001BISQE	NSC	获取价格	Low-Noise Clock Jitter Cleaner with Cascaded PLLs

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