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LMK04002BISQE PDF预览

LMK04002BISQE

更新时间： 2024-11-14 11:37:19
品牌 Logo 应用领域
美国国家半导体 - NSC 逻辑集成电路信息通信管理驱动PC时钟
页数 文件大小 规格书
54页 1171K
描述
Low-Noise Clock Jitter Cleaner with Cascaded PLLs

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中文翻译

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LMK04002BISQE 技术参数

是否Rohs认证： 不符合生命周期：Transferred
包装说明：HVQCCN, LCC48,.27SQ,20Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.35
系列：4000/14000/40000输入调节：DIFFERENTIAL MUX
JESD-30 代码：S-XQCC-N48长度：7 mm
逻辑集成电路类型：PLL BASED CLOCK DRIVER最大I（ol）：0.0005 A
湿度敏感等级：1功能数量：1
反相输出次数：端子数量：48
实输出次数：5最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
封装主体材料：UNSPECIFIED封装代码：HVQCCN
封装等效代码：LCC48,.27SQ,20封装形状：SQUARE
封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度（摄氏度）：225
电源：3.3 V认证状态：Not Qualified
Same Edge Skew-Max（tskwd）：0.1 ns座面最大高度：0.8 mm
子类别：Clock Drivers最大供电电压 (Vsup)：3.45 V
最小供电电压 (Vsup)：3.15 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：BICMOS
温度等级：INDUSTRIAL端子形式：NO LEAD
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：7 mm
Base Number Matches：1

LMK04002BISQE 数据手册

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September 10, 2010  
LMK04000 Family  
Low-Noise Clock Jitter Cleaner with Cascaded PLLs  
1.0 General Description  
2.0 Features  
The LMK04000 family of precision clock conditioners pro-  
vides low-noise jitter cleaning, clock multiplication and distri-  
bution without the need for high-performance voltage con-  
trolled crystal oscillators (VCXO) module. Using a cascaded  
PLLatinum™ architecture combined with an external crystal  
and varactor diode, the LMK04000 family provides sub-200  
femtosecond (fs) root mean square (RMS) jitter performance.  
Cascaded PLLatinum PLL Architecture  
■
PLL1  
—
Phase detector rate of up to 40 MHz  
■
■
■
Integrated Low-Noise Crystal Oscillator Circuit  
Dual redundant input reference clock with LOS  
PLL2  
—
Normalized [1 Hz] PLL noise floor of -224 dBc/Hz  
■
■
■
■
The cascaded architecture consists of two high-performance  
phase-locked loops (PLL), a low-noise crystal oscillator cir-  
cuit, and a high-performance voltage controlled oscillator  
(VCO). The first PLL (PLL1) provides a low-noise jitter cleaner  
function while the second PLL (PLL2) performs the clock gen-  
eration. PLL1 can be configured to either work with an exter-  
nal VCXO module or use the integrated crystal oscillator with  
an external crystal and a varactor diode. When used with a  
very narrow loop bandwidth, PLL1 uses the superior close-in  
phase noise (offsets below 50 kHz) of the VCXO module or  
the crystal to clean the input clock. The output of PLL1 is used  
as the clean input reference to PLL2 where it locks the inte-  
grated VCO. The loop bandwidth of PLL2 can be optimized  
to clean the far-out phase noise (offsets above 50 kHz) where  
the integrated VCO outperforms the VCXO module or crystal  
used in PLL1.  
Phase detector rate up to 100 MHz  
Input frequency-doubler  
Integrated Low-Noise VCO  
Ultra-Low RMS Jitter Performance  
■
150 fs RMS jitter (12 kHz – 20 MHz)  
200 fs RMS jitter (100 Hz – 20 MHz)  
—
—
LVPECL/2VPECL, LVDS, and LVCMOS outputs  
■
■
■
■
■
■
■
■
Support clock rates up to 1080 MHz  
Default Clock Output (CLKout2) at power up  
Five dedicated channel divider and delay blocks  
Pin compatible family of clocking devices  
Industrial Temperature Range: -40 to 85 °C  
3.15 V to 3.45 V operation  
The LMK04000 family features dual redundant inputs, five  
differential outputs, and an optional default-clock upon power  
up. The input block is equipped with loss of signal detection  
and automatic or manual selection of the reference clock.  
Each clock output consists of a programmable divider, a  
phase synchronization circuit, a programmable delay, and an  
LVDS, LVPECL, or LVCMOS output buffer. The default start-  
up clock is available on CLKout2 and it can be used to provide  
an initial clock for the field-programmable gate array (FPGA)  
or microcontroller that programs the jitter cleaner during the  
system power up sequence.  
Package: 48 pin LLP (7.0 x 7.0 x 0.8 mm)  
3.0 Target Applications  
Data Converter Clocking  
■
■
■
■
■
■
■
Wireless Infrastructure  
Networking, SONET/SDH, DSLAM  
Medical  
Military / Aerospace  
Test and Measurement  
Video  
30027140  
PLLatinum™ is a trademark of National Semiconductor Corporation.  
TRI-STATE® is a registered trademark of National Semiconductor Corporation.  
© 2010 National Semiconductor Corporation  
300271  
www.national.com  
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中文翻译

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与LMK04002BISQE相关器件

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LMK04002BISQE/NOPB TI

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 		具有 1600MHz 至 1750MHz VCO 的低噪声抖动消除器：3 路输出用于 2V
LMK04002BISQX NSC

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 		Low-Noise Clock Jitter Cleaner with Cascaded PLLs
LMK04002BISQX/NOPB TI

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 		具有 1600MHz 至 1750MHz VCO 的低噪声抖动消除器：3 路输出用于 2V
LMK04010 TI

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 		具有 1185 至 1296MHz VCO 的低噪声抖动消除器：5 路输出用于 2VPEC
LMK04010BISQ NSC

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 		Low-Noise Clock Jitter Cleaner with Cascaded PLLs
LMK04010BISQ/NOPB TI

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 		具有 1185 至 1296MHz VCO 的低噪声抖动消除器：5 路输出用于 2VPEC
LMK04010BISQE NSC

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 		Low-Noise Clock Jitter Cleaner with Cascaded PLLs
LMK04010BISQE/NOPB TI

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 		具有 1185 至 1296MHz VCO 的低噪声抖动消除器：5 路输出用于 2VPEC
LMK04010BISQX NSC

获取价格

 		Low-Noise Clock Jitter Cleaner with Cascaded PLLs
LMK04010BISQX/NOPB TI

获取价格

 		具有 1185 至 1296MHz VCO 的低噪声抖动消除器：5 路输出用于 2VPEC

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