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LMK04031BISQX/NOPB PDF预览

LMK04031BISQX/NOPB

更新时间： 2024-11-15 11:13:03
品牌 Logo 应用领域
德州仪器 - TI 驱动信息通信管理逻辑集成电路
页数 文件大小 规格书
66页 1150K
描述
具有 1430MHz 至 1570MHz VCO 的低噪声抖动消除器：2 路输出用于 2VPEC/LVPEC+LVDS+LVCMOS | RHS | 48 | -40 to 85

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LMK04031BISQX/NOPB 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFN
包装说明：HVQCCN, LCC48,.27SQ,20针数：48
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：1.78
系列：4000/14000/40000输入调节：DIFFERENTIAL MUX
JESD-30 代码：S-XQCC-N48JESD-609代码：e3
长度：7 mm负载电容（CL）：10 pF
逻辑集成电路类型：PLL BASED CLOCK DRIVER最大I（ol）：0.0005 A
湿度敏感等级：3功能数量：1
反相输出次数：端子数量：48
实输出次数：5最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
封装主体材料：UNSPECIFIED封装代码：HVQCCN
封装等效代码：LCC48,.27SQ,20封装形状：SQUARE
封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE包装方法：TR
峰值回流温度（摄氏度）：260电源：3.3 V
认证状态：Not QualifiedSame Edge Skew-Max（tskwd）：0.1 ns
座面最大高度：0.8 mm子类别：Clock Drivers
最大供电电压 (Vsup)：3.45 V最小供电电压 (Vsup)：3.15 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：BICMOS温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：NO LEAD
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：7 mm
最小 fmax：1570 MHz

LMK04031BISQX/NOPB 数据手册

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LMK04000, LMK04001, LMK04002, LMK04010  
LMK04011, LMK04031, LMK04033  
www.ti.com  
SNOSAZ8J –SEPTEMBER 2008–REVISED SEPTEMBER 2011  
LMK04000 Family Low-Noise Clock Jitter Cleaner with Cascaded PLLs  
Check for Samples: LMK04000, LMK04001, LMK04002, LMK04010, LMK04011, LMK04031, LMK04033  
1
FEATURES  
23  
•
Cascaded PLLatinum™ PLL Architecture  
•
•
•
Support Clock Rates up to 1080 MHz  
–
PLL1  
Default Clock Output (CLKout2) at power up  
–
–
Phase Detector Rate of up to 40 MHz  
Five Dedicated Channel Divider and Delay  
Blocks  
Integrated Low-Noise Crystal Oscillator  
Circuit  
•
•
•
•
Pin Compatible Family of Clocking Devices  
Industrial Temperature Range: -40 to 85 °C  
3.15 V to 3.45 V Operation  
–
Dual Redundant Input Reference Clock  
with LOS  
–
PLL2  
Package: 48 Pin WQFN (7.0 x 7.0 x 0.8 mm)  
–
Normalized [1 Hz] PLL Noise Floor of -  
224 dBc/Hz  
APPLICATIONS  
–
–
–
Phase Detector Rate up to 100 MHz  
Input Frequency-Doubler  
Integrated Low-Noise VCO  
•
•
•
•
•
•
•
Data Converter Clocking  
Wireless Infrastructure  
Networking, SONET/SDH, DSLAM  
Medical  
•
•
Ultra-Low RMS Jitter Performance  
–
–
150 fs RMS Jitter (12 kHz – 20 MHz)  
200 fs RMS Jitter (100 Hz – 20 MHz)  
Military / Aerospace  
Test and Measurement  
Video  
LVPECL/2VPECL, LVDS, and LVCMOS outputs  
DESCRIPTION  
The LMK04000 family of precision clock conditioners provides low-noise jitter cleaning, clock multiplication and  
distribution without the need for high-performance voltage controlled crystal oscillators (VCXO) module. Using a  
cascaded PLLatinum™ architecture combined with an external crystal and varactor diode, the LMK04000 family  
provides sub-200 femtosecond (fs) root mean square (RMS) jitter performance.  
The cascaded architecture consists of two high-performance phase-locked loops (PLL), a low-noise crystal  
oscillator circuit, and a high-performance voltage controlled oscillator (VCO). The first PLL (PLL1) provides a low-  
noise jitter cleaner function while the second PLL (PLL2) performs the clock generation. PLL1 can be configured  
to either work with an external VCXO module or use the integrated crystal oscillator with an external crystal and  
a varactor diode. When used with a very narrow loop bandwidth, PLL1 uses the superior close-in phase noise  
(offsets below 50 kHz) of the VCXO module or the crystal to clean the input clock. The output of PLL1 is used as  
the clean input reference to PLL2 where it locks the integrated VCO. The loop bandwidth of PLL2 can be  
optimized to clean the far-out phase noise (offsets above 50 kHz) where the integrated VCO outperforms the  
VCXO module or crystal used in PLL1.  
The LMK04000 family features dual redundant inputs, five differential outputs, and an optional default-clock upon  
power up. The input block is equipped with loss of signal detection and automatic or manual selection of the  
reference clock. Each clock output consists of a programmable divider, a phase synchronization circuit, a  
programmable delay, and an LVDS, LVPECL, or LVCMOS output buffer. The default startup clock is available on  
CLKout2 and it can be used to provide an initial clock for the field-programmable gate array (FPGA) or  
microcontroller that programs the jitter cleaner during the system power up sequence.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
3
PLLatinum is a trademark of Texas Instruments.  
All other trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2008–2011, Texas Instruments Incorporated  
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与LMK04031BISQX/NOPB相关器件

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LMK04033 TI

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 		具有 1840MHz 至 2160MHz VCO 的低噪声抖动消除器：2 路输出用于 2V
LMK04033BISQ NSC

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 		Low-Noise Clock Jitter Cleaner with Cascaded PLLs
LMK04033BISQ/NOPB TI

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 		具有 1840MHz 至 2160MHz VCO 的低噪声抖动消除器：2 路输出用于 2V
LMK04033BISQE NSC

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 		Low-Noise Clock Jitter Cleaner with Cascaded PLLs
LMK04033BISQE/NOPB TI

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 		具有 1840MHz 至 2160MHz VCO 的低噪声抖动消除器：2 路输出用于 2V
LMK04033BISQX NSC

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 		Low-Noise Clock Jitter Cleaner with Cascaded PLLs
LMK04033BISQX/NOPB TI

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 		具有 1840MHz 至 2160MHz VCO 的低噪声抖动消除器：2 路输出用于 2V
LMK04100 TI

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 		LMK04100 Family Clock Jitter Cleaner with Cascaded PLLs
LMK04100SQ/NOPB TI

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 		具有级联 PLL 的精密时钟调节器时钟抖动消除器 | RHS | 48 | -40 to
LMK04100SQE/NOPB TI

获取价格

 		具有级联 PLL 的精密时钟调节器时钟抖动消除器 | RHS | 48 | -40 to

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