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LMK04102 PDF预览

LMK04102

更新时间: 2024-11-15 11:13:35
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
53页 817K
描述
具有集成式 1600MHz 至 1750MHz VCO 的抖动消除器:3 路输出用于 2VPEC/LVPEC+4 路输出用于 LVCMOS

LMK04102 数据手册

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LMK04100, LMK04101, LMK04102, LMK04110  
LMK04111, LMK04131, LMK04133  
www.ti.com  
SNAS516B APRIL 2011REVISED NOVEMBER 2012  
LMK04100 Family Clock Jitter Cleaner with Cascaded PLLs  
Check for Samples: LMK04100, LMK04101, LMK04102, LMK04110, LMK04111, LMK04131, LMK04133  
1
FEATURES  
23  
Cascaded PLLatinum™ PLL Architecture  
Industrial Temperature Range: -40 to 85 °C  
3.15 V to 3.45 V Operation  
PLL1  
Redundant Reference Inputs  
Package: 48 Pin WQFN (7.0 x 7.0 x 0.8 mm)  
Loss of Signal Detection  
APPLICATIONS  
Automatic and Manual Selection of  
Reference Clock Input  
Multi-Carrier/Multi-Mode/Multi-Band 2G/3G/4G  
Basestations  
PLL2  
Cellular Repeaters  
Phase Detector Rate up to 100 MHz  
High Speed A/D clocking  
Input Frequency-Doubler  
Integrated VCO  
SONET/SDH OC-48/OC-192/OC-768 Line Cards  
GbE/10GbE, 1/2/4/8/10G Fibre Channel Line  
Cards  
Outputs  
LVPECL/2VPECL, LVDS, and LVCMOS  
Formats  
Optical Transport Networks  
Broadcast Video, HDTV  
Serial ATA  
Support Clock Rates up to 1080 MHz  
Five Dedicated Channel Divider Blocks  
Common Output Frequencies Supported:  
DESCRIPTION  
30.72 MHz, 61.44 MHz, 62.5 MHz, 74.25  
MHz, 75 MHz, 77.76 MHz, 100 MHz,  
106.25 MHz, 125 MHz, 122.88 MHz, 150  
MHz, 155.52 MHz, 156.25 MHz, 159.375  
MHz, 187.5 MHz, 200 MHz, 212.5 MHz,  
245.76 MHz, 250 MHz, 311.04 MHz, 312.5  
MHz, 368.64 MHz, 491.52 MHz, 622.08  
MHz, 625 MHz, 983.04 MHz  
The LMK04100 family of precision clock conditioners  
provides jitter cleaning, clock multiplication and  
distribution without the need for high-performance  
VCXO modules.  
When connected to a recovered system reference  
clock and a VCXO, the device generates 5 low jitter  
clocks in LVCMOS, LVDS, or LVPECL formats.  
MICROWIRE (SPI) Programming Interface  
External VCXO or  
low cost crystal  
OSCin (Single ended or differential)  
CLKout4  
Internal  
VCO  
CLKin0  
PLL2  
PLL1  
CLKout3  
CLKin1  
CLKout2  
CLK  
CLKout1  
CLKout0  
mWire  
DATA  
Port  
LE  
SYNC*  
GOE  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
3
PLLatinum is a trademark of Texas Instruments.  
All other trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2011–2012, Texas Instruments Incorporated  

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