March 26, 2008
LMK03000 Family
Precision Clock Conditioner with Integrated VCO
General Description
Features
The LMK03000 family of precision clock conditioners com-
bine the functions of jitter cleaning/reconditioning, multiplica-
tion, and distribution of a reference clock. The devices
integrate a Voltage Controlled Oscillator (VCO), a high per-
formance Integer-N Phase Locked Loop (PLL), a partially
integrated loop filter, and up to eight outputs in various LVDS
and LVPECL combinations.
Integrated VCO with very low phase noise floor
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Integrated Integer-N PLL with outstanding normalized
phase noise contribution of -224 dBc/Hz
VCO divider values of 2 to 8 (all divides)
Channel divider values of 1, 2 to 510 (even divides)
3 LVDS and 5 LVPECL clock outputs
Partially integrated loop filter
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The VCO output is optionally accessible on the Fout port. In-
ternally, the VCO output goes through a VCO Divider to feed
the various clock distribution blocks.
Dedicated divider and delay blocks on each clock output
Pin compatible family of clocking devices
3.15 to 3.45 V operation
Each clock distribution block includes a programmable di-
vider, a phase synchronization circuit, a programmable delay,
a clock output mux, and an LVDS or LVPECL output buffer.
This allows multiple integer-related and phase-adjusted
copies of the reference to be distributed to eight system com-
ponents.
Package: 48 pin LLP (7.0 x 7.0 x 0.8 mm)
200 fs RMS Clock generator performance (10 Hz to 20
MHz) with a clean input clock
VCO Frequency
Range (MHz)
The clock conditioners come in a 48-pin LLP package and are
footprint compatible with other clocking devices in the same
family.
Part
RMS Jitter (fs)
LMK03000C
LMK03000
LMK03000D
LMK03001C
LMK03001
LMK03001D
400
800
1185 - 1296
Target Applications
1200
400
Data Converter Clocking
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Networking, SONET/SDH, DSLAM
1470 - 1570
800
Wireless Infrastructure
1200
Medical
Test and Measurement
Military / Aerospace
System Diagram
20211440
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202114
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