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LMK03002ISQ PDF预览

LMK03002ISQ

更新时间: 2024-11-14 03:51:43
品牌 Logo 应用领域
美国国家半导体 - NSC 调节器时钟
页数 文件大小 规格书
24页 477K
描述
Precision Clock Conditioner with Integrated VCO

LMK03002ISQ 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:7 X 7 MM, 0.80 MM HEIGHT, LLP-48Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.27JESD-30 代码:S-XQCC-N48
JESD-609代码:e0长度:7 mm
湿度敏感等级:2端子数量:48
最高工作温度:85 °C最低工作温度:-40 °C
最大输出时钟频率:862 MHz封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE主时钟/晶体标称频率:200 MHz
认证状态:Not Qualified座面最大高度:0.8 mm
最大供电电压:3.45 V最小供电电压:3.15 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
宽度:7 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHER
Base Number Matches:1

LMK03002ISQ 数据手册

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August 2007  
LMK03002/LMK03002C  
Precision Clock Conditioner with Integrated VCO  
General Description  
Features  
The LMK03002/LMK03002C precision clock conditioners  
combine the functions of jitter cleaning/reconditioning, multi-  
plication, and distribution of a reference clock. The devices  
integrate a Voltage Controlled Oscillator (VCO), a high per-  
formance Integer-N Phase Locked Loop (PLL), a partially  
integrated loop filter, and four LVPECL clock output distribu-  
tion blocks.  
Integrated VCO with very low phase noise floor  
Integrated Integer-N PLL with outstanding normalized  
phase noise contribution of -224 dBc/Hz  
Clock generator performance (10 Hz - 20 MHz)  
LMK03002C: 200 fs RMS jitter  
Jitter cleaner performance grade (12 kHz to 20 MHz)  
The VCO output is optionally accessible on the Fout port. In-  
ternally, the VCO output goes through a VCO Divider to feed  
the various clock distribution blocks.  
LMK03002: 800 fs RMS jitter  
LMK03002C: 400 fs RMS jitter  
VCO frequency: 1566 to 1724 MHz  
Clock output frequency range of 1 to 862 MHz  
4 LVPECL clock outputs  
Each clock distribution block includes a programmable di-  
vider, a phase synchronization circuit, a programmable delay,  
a clock output mux, and an LVPECL output buffer. This allows  
multiple integer-related and phase-adjusted copies of the ref-  
erence to be distributed to four system components.  
Partially integrated loop filter  
Dedicated divider and delay blocks on each clock output  
Pin compatible family of clocking devices  
3.15 to 3.45 V operation  
The clock conditioners come in a 48-pin LLP package and are  
footprint compatible with other clocking devices in the same  
family.  
Package: 48 pin LLP (7.0 x 7.0 x 0.8 mm)  
Target Applications  
Data Converter Clocking  
Networking, SONET/SDH, DSLAM  
Wireless Infrastructure  
Medical  
Test and Measurement  
Military / Aerospace  
TRI-STATE® is a registered trademark of National Semiconductor Corporation.  
© 2007 National Semiconductor Corporation  
300206  
www.national.com  

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