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LM9618

更新时间: 2024-11-08 22:47:03
品牌 Logo 应用领域
美国国家半导体 - NSC 传感器图像传感器
页数 文件大小 规格书
2页 90K
描述
Monochrome CMOS Image Sensor VGA 30 FPS

LM9618 数据手册

 浏览型号LM9618的Datasheet PDF文件第2页 
ADVANCE INFORMATION  
May 2002  
LM9618 Monochrome CMOS Image Sensor VGA 30 FPS  
General Description  
Applications  
The LM9618 is a high performance, low power, 1/3” VGA CMOS  
Active Pixel Sensor capable of capturing grey-scale digital still or  
motion images and converting them to a digital data stream.  
f Security Cameras  
f Machine Vision  
f Automotive  
f Biometrics  
f IR imaging  
In addition to the active pixel array, an on-chip 12 bit A/D conver-  
tor, fixed pattern noise elimination circuits, a video gain and sep-  
arate color gain are provided. Furthermore, an integrated  
programmable smart timing and control circuit allows the user  
maximum flexibility in adjusting integration time, active window  
size, gain and frame rate. Various control, timing and power  
modes are also provided.  
f Barcode Scanners  
Key Specifications  
Array Format  
Total:  
Active: 648H x 488 V  
664H x 504V  
The excellent linear dynamic range of the sensor can be  
Effective Image Area  
Total: 4.98mm x 3.78 mm  
Active: 4.86 mm x 3.66 mm  
extended to above 100dB by programming  
a non linear  
response curve that matches the response of the human eye.  
Optical Format  
Pixel Size  
1/3“  
7.5mm x 7.5mm  
8,10 & 12 Bit Digital  
30 frames per second  
Features  
f Video or snapshot operations  
Video Outputs  
Frame Rate  
f Progressive scan and interlace read out modes.  
f Programmable pixel clock, inter-frame and inter-line delays.  
f Programmable partial or full frame integration  
f Programmable gain and individual color gain  
f Horizontal & vertical sub-sampling (2:1 & 4:2)  
f Programmable digital video response curve  
f Windowing  
Dynamic Range  
62dB in linear mode  
110dB in non linear mode  
Electronic Shutter  
Rolling reset  
0.1%  
FPN  
PRMU  
1.5%  
Sensitivity  
5 V/lux.s  
27%  
f External snapshot trigger & event synchronisation signals  
f Auto black level compensation  
f Flexible digital video read-out supporting programmable:  
Quantum Efficiency  
Fill Factor  
47%  
-
-
polarity for synchronisation and pixel clock signals  
Package  
48 CLCC  
3.3 V +/-10%  
120 mW  
-40 to 85oC  
leading edge adjustment for horizontal synchronization  
Single Supply  
Power Consumption  
Operating Temp  
2
f Programmable via 2 wire I C compatible serial interface  
f Power on reset & power down mode  
Overall Chip Block Diagram  
oe  
R
d[11:0]  
pclk  
12 Bit A/D  
AMP  
G
B
MUX  
Row Address  
Decoder  
hsync  
vsync  
APS Array  
POR  
Horizontal  
Timing  
Reset  
Gen  
Vertical  
Timing  
Gain  
Control  
Row Address  
Gen  
sda  
sclk  
2
I C Compatible  
Serial I/F  
Register Bank  
Power  
Control  
Clock Gen  
Controller  
(sequencer)  
sadr  
Master Timer  
reset mclk  
extsync  
pdwn  
snapshot  
ã 2002 National Semiconductor Corporation  
www.national.com  

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