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LE58083ABGC PDF预览

LE58083ABGC

更新时间: 2024-11-23 20:05:23
品牌 Logo 应用领域
美高森美 - MICROSEMI PC电信电信集成电路
页数 文件大小 规格书
95页 981K
描述
PCM Codec, A/MU-Law, 1-Func, CMOS, PBGA121, GREEN, M0-219B, LFBGA-121

LE58083ABGC 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:BGA
包装说明:LFBGA,针数:121
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.73其他特性:IT ALSO OPERATES WITH 3.3V ANALOG SUPPLY VOLTAGE
压伸定律:A/MU-LAW滤波器:YES
JESD-30 代码:S-PBGA-B121长度:10 mm
功能数量:1端子数量:121
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:LFBGA封装形状:SQUARE
封装形式:GRID ARRAY, LOW PROFILE, FINE PITCH认证状态:Not Qualified
座面最大高度:1.4 mm标称供电电压:3.3 V
表面贴装:YES技术:CMOS
电信集成电路类型:PCM CODEC温度等级:INDUSTRIAL
端子形式:BALL端子节距:0.8 mm
端子位置:BOTTOM宽度:10 mm
Base Number Matches:1

LE58083ABGC 数据手册

 浏览型号LE58083ABGC的Datasheet PDF文件第2页浏览型号LE58083ABGC的Datasheet PDF文件第3页浏览型号LE58083ABGC的Datasheet PDF文件第4页浏览型号LE58083ABGC的Datasheet PDF文件第5页浏览型号LE58083ABGC的Datasheet PDF文件第6页浏览型号LE58083ABGC的Datasheet PDF文件第7页 
Le58083  
Low Voltage Subscriber Line Audio-processing Circuit  
VE580 Series  
APPLICATIONS  
RELATED LITERATURE  
Codec function on telephone switch line cards  
080753 Le58QL02/021/031 QLSLACData Sheet  
080754 Le58QL061/063 QLSLACData Sheet  
FEATURES  
080761 QSLAC™ to QLSLAC™ Design Conversion  
Low-power, 3.3 V CMOS technology with 5 V tolerant  
Guide  
digital inputs  
080758 QSLAC™ to QLSLAC™ Guide to New Designs  
Pin programmable PCM/MPI or GCI interface  
Software and coefficient compatible to the VE580  
DESCRIPTION  
series QLSLAC™ devices  
The Le58083 Octal Low Voltage Subscriber Line Audio-  
Processing Circuit (Octal SLAC™) devices integrate the key  
functions of analog line cards into high-performance, very-  
programmable, eight-channel codec-filter devices. The  
Le58083 Octal SLAC devices are based on the proven design  
of Zarlink’s reliable SLAC device families. The advanced  
architecture of the Le58083 Octal SLAC devices implements  
eight independent channels and employs digital filters to allow  
software control of transmission, thus providing a cost-effective  
solution for the audio-processing function of programmable line  
cards. The Le58083 Octal SLAC devices are software and  
coefficient compatible to the VE580 series QLSLAC™ devices.  
Advanced submicron CMOS technology makes the Le58083  
Octal SLAC devices economical, with both the functionality and  
the low power consumption needed in line card designs to  
maximize line card density at minimum cost. When used with  
multiple Zarlink SLIC devices, an Le58083 Octal SLAC device  
provides a complete software-configurable solution to the  
BORSCHT functions.  
Standard PCM/microprocessor interface  
(PCM/MPI mode)  
— Single or Dual PCM ports available  
— Time slot assigner (up to 128 channels per port)  
— Clock slot and transmit clock edge options  
— Optional supervision on the PCM highway  
— 1.536, 1.544, 2.048, 3.072, 3.088, 4.096, 6.144, 6.176,  
or 8.192 MHz master clock derived from MCLK or PCLK  
— µP access to PCM data  
— Real Time Data with interrupt (open drain or TTL)  
— Broadcast mode  
General Circuit Interface (GCI mode)  
— Control and PCM data on a single port  
— 2.048 Mbits/s data rate  
— 2.048 MHz or 4.096 MHz clock option  
Performs the functions of eight codec/filters  
Software programmable:  
— SLIC device input impedance and Transhybrid balance  
— Transmit and receive gains and Equalization  
— Programmable Digital I/O pins with debouncing  
A-law, µ-law, or linear coding  
BLOCK DIAGRAM  
GCI/PCM  
Interface  
ANALOG  
DXA/DU  
DRA/DD  
TSCA  
DXB  
Built-in test modes with loopback, tone generation,  
VIN(1-8)  
and µP access to PCM data  
Signal  
Processing  
Channels 1-8  
PCM & GCI Interface  
&
VOUT(1-8)  
Mixed state (analog and digital) impedance scaling  
Performance guaranteed over a 12 dB gain range  
Supports multiplexed SLIC device outputs  
DRB  
Time Slot Assigner  
(TSA)  
TSCB  
VREF_1, VREF_2  
256 kHz or 293 kHz chopper clock for Zarlink SLIC  
SLIC  
CONTROLS  
Clock  
&
Reference  
Circuits  
devices with switching regulator  
FS/FSC  
CD1(1-8)  
CD2(1-8)  
C3(1-8)  
PCLK/DCL  
Maximum channel bandwidth for V.90 modems  
MCLK_1, MCLK_2  
SLIC  
Interface  
(SLI)  
ORDERING INFORMATION  
C4(1-8)  
C5(1-8)  
DCLK-S0_1, DCLK-SO_2  
CS/PG_1, CS/PG_2  
Device  
Package  
GCI Control Logic &  
Microprocessor Interface  
(MPI)  
C6(1-8)  
C7(1-8)  
DIO-S1_1, DIO-S1_2  
Le58083ABGC  
121-pin BGA (Green package)*  
INT_1, INT_2  
RST  
*Green package meets RoHS Directive 2002/95/EC of the European  
Council to minimize the environmental impact of electrical equipment.  
Document ID# 080921 Date:  
Sep 18, 2007  
2
Rev:  
E
Version:  
Distribution:  
Public Document  
 
 
 
 
 
 

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