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LE58QL061BVC PDF预览

LE58QL061BVC

更新时间: 2024-11-26 21:11:59
品牌 Logo 应用领域
美高森美 - MICROSEMI PC电信电信集成电路
页数 文件大小 规格书
108页 983K
描述
PCM Codec, A/MU-Law, 1-Func, CMOS, PQFP44, GREEN, MS-026ACB, TQFP-44

LE58QL061BVC 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFP
包装说明:TQFP, TQFP44,.47SQ,32针数:44
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.29其他特性:IT ALSO OPERATES WITH 3.3V ANALOG SUPPLY VOLTAGE
压伸定律:A/MU-LAW滤波器:YES
最大增益公差:0.4 dBJESD-30 代码:S-PQFP-G44
JESD-609代码:e3长度:10 mm
线性编码:16-BIT功能数量:1
端子数量:44工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:TQFP
封装等效代码:TQFP44,.47SQ,32封装形状:SQUARE
封装形式:FLATPACK, THIN PROFILE电源:3.3 V
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Codecs标称供电电压:3.3 V
表面贴装:YES技术:CMOS
电信集成电路类型:PCM CODEC温度等级:INDUSTRIAL
端子面层:MATTE TIN端子形式:GULL WING
端子节距:0.8 mm端子位置:QUAD
宽度:10 mmBase Number Matches:1

LE58QL061BVC 数据手册

 浏览型号LE58QL061BVC的Datasheet PDF文件第2页浏览型号LE58QL061BVC的Datasheet PDF文件第3页浏览型号LE58QL061BVC的Datasheet PDF文件第4页浏览型号LE58QL061BVC的Datasheet PDF文件第5页浏览型号LE58QL061BVC的Datasheet PDF文件第6页浏览型号LE58QL061BVC的Datasheet PDF文件第7页 
Le58QL061/063  
Quad Low Voltage Subcriber Line  
Audio-Processing Circuit - Ve580 Series  
Data Sheet  
Document ID#: 080754  
Version 8  
June 2011  
Features  
Low-power, 3.3 V CMOS technology with 5 V  
tolerant digital inputs  
Ordering Information  
Device  
Package1 (Green) Packing2  
Pin programmable PCM/MPI or GCI interface  
Le58QL061BVC  
Le58QL063HVC  
44-pin TQFP  
64-pin LQFP  
Trays  
Trays  
Software and coefficient compatible to the  
Le79Q061/063 QSLAC device  
1. The green package meets RoHS Directive 2002/95/EC of the  
European Council to minimize the environmental impact of  
electrical equipment.  
Standard PCM/microprocessor interface  
(PCM/MPI mode)  
2. For delivery using a tape and reel packing system, add a "T"  
suffix to the OPN (Ordering Part Number) when placing an  
order.  
Single or Dual PCM ports available  
Time slot assigner (up to 128 channels per  
port)  
256 kHz or 293 kHz chopper clock for Zarlink  
SLIC devices with switching regulator  
Clock slot and transmit clock edge options  
Optional supervision on the PCM highway  
Maximum channel bandwidth for V.90 modems  
1.536, 1.544, 2.048, 3.072, 3.088, 4.096,  
6.144, 6.176, or 8.192 MHz master clock  
derived from MCLK or PCLK  
Applications  
Codec function on telephone switch line cards  
µP access to PCM data  
Real Time Data with interrupt (open drain or  
TTL)  
GCI/PCM  
Interface  
Analog  
VIN1  
DXA/DU  
DRA/DD  
TSCA  
DXB  
Signal Processing  
Channel 1 (CH 1)  
Broadcast mode  
VOUT1  
PMC & GCI Interface  
&
VIN2  
Signal Processing  
Channel 2 (CH 2)  
General Circuit Interface (GCI mode)  
Time Slot Assigner  
(TSA)  
VOUT2  
DRB  
VIN3  
Control and PCM data on a single port  
2.048 Mbits/s data rate  
Signal Processing  
Channel 3 (CH 3)  
TSCB  
VOUT3  
VIN4  
Signal Processing  
Channel 4 (CH 4)  
VOUT4  
VREF  
SLIC  
2.048 MHz or 4.096 MHz clock option  
Clock  
&
Reference  
Circuits  
CD11  
CD21  
C31  
Performs the functions of four codec/filters  
Software programmable:  
C41  
FS/FSC  
C51  
PCLK/DCL  
MCLK/E1  
C61  
C71  
SLIC device input impedance and Transhybrid  
balance  
CD12  
CD22  
C32  
C42  
Transmit and receive gains and Equalization  
C52  
C62  
C72  
SLIC  
Interface  
(SLI)  
Programmable Digital I/O pins with  
debouncing  
DCLK/S0  
CD13  
CD23  
CS/PG  
DIO/S1  
GCI Control Logic &  
Microprocessor Interface  
(MPI)  
C33  
C43  
C53  
C63  
C73  
INT  
A-law, µ-law, or linear coding  
RST  
CD14  
CD24  
Built-in test modes with loopback, tone  
generation, and µP access to PCM data  
C34  
C44  
C54  
C64  
Mixed state (analog and digital) impedance  
scaling  
C74  
CHCLK  
Performance guaranteed over a 12 dB gain range  
Supports multiplexed SLIC device outputs  
Figure 1 - Block Diagram  
1
Zarlink Semiconductor Inc.  
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.  
Copyright 2009-2011, Zarlink Semiconductor Inc. All Rights Reserved.  
 

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