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LE58QL031JC PDF预览

LE58QL031JC

更新时间： 2024-11-24 10:22:31
品牌 Logo 应用领域
美高森美 - MICROSEMI PC电信电信集成电路
页数 文件大小 规格书
66页 1217K
描述
PCM Codec, A/MU-Law, 1-Func, CMOS, PQCC32, PLASTIC, MS-016, LCC-32

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中文翻译

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LE58QL031JC 数据手册

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™
Le58QL02/021/031  
Quad Low Voltage Subscriber Line Audio-Processing Circuit  
VE580 Series  
APPLICATIONS  
ORDERING INFORMATION  
Device  
Package (Green)1  
44-pin PLCC  
Packing2  
„ Codec function on telephone switch line cards  
FEATURES  
Le58QL02FJC  
Le58QL021FJC  
Le58QL021BVC  
Le58QL031DJC  
Tube  
Tube  
Tray  
44-pin PLCC  
44-pin TQFP  
32-pin PLCC  
„ Low-power, 3.3 V CMOS technology with 5-V tolerant  
digital inputs  
Tube  
„ Software and coefficient compatible to the Le79Q02/  
1. The green package meets RoHS Directive 2002/95/EC of the  
European Council to minimize the environmental impact of  
electrical equipment.  
021/031 QSLAC™ device  
„ Performs the functions of four codec/filters  
„ Software programmable:  
— SLIC device input impedance  
— Transhybrid balance  
2. For delivery using a tape and reel packing system, add a "T" suffix  
to the OPN (Ordering Part Number) when placing an order.  
DESCRIPTION  
— Transmit and receive gains  
— Equalization (frequency response)  
— Digital I/O pins  
— Programmable debouncing on one input  
— Time slot assigner  
The Le58QL02/021/031 Quad Low Voltage Subscriber Line  
Audio-Processing Circuit (QLSLAC™) devices integrate the  
key functions of analog line cards into high-performance, very-  
programmable, four-channel codec-filter devices. The  
QLSLAC devices are based on the proven design of Legerity’s  
reliable SLAC™ device families. The advanced architecture of  
the QLSLAC devices implements four independent channels  
and employs digital filters to allow software control of  
transmission, thus providing a cost-effective solution for the  
audio-processing function of programmable line cards. The  
QLSLAC devices are software and coefficient compatible to the  
QSLAC devices.  
— Programmable clock slot and PCM transmit clock edge  
options  
„ Standard microprocessor interface  
„ A-law, µ-law, or linear coding  
„ Single or Dual PCM ports available  
— Up to 128 channels (PCLK at 8.192 MHz) per PCM port  
— Optional supervision on the PCM highway  
Advanced submicron CMOS technology makes the Le58QL02/  
021/031 QLSLAC devices economical, with both the  
functionality and the low power consumption needed in line  
card designs to maximize line card density at minimum cost.  
When used with four Legerity SLIC devices, a QLSLAC device  
provides a complete software-configurable solution to the  
BORSCHT functions.  
„ 1.536, 1.544, 2.048, 3.072, 3.088, 4.096, 6.144, 6.176, or  
8.192 MHz master clock derived from MCLK or PCLK  
„ Built-in test modes with loopback, tone generation,  
and µP access to PCM data  
„ Mixed state (analog and digital) impedance scaling  
„ Performance guaranteed over a 12 dB gain range  
BLOCK DIAGRAM  
„ Real Time Data register with interrupt (open drain or  
Dual/Single  
PCM  
Highway  
TTL output)  
Analog  
VIN1  
DXA  
DRA  
TSCA  
DXB  
„ Supports multiplexed SLIC device outputs  
„ Broadcast state  
Signal Processing  
Channel 1 (CH 1)  
VOUT1  
Time Slot Assigner  
(TSA)  
VIN2  
Signal Processing  
Channel 2 (CH 2)  
VOUT2  
DRB  
TSCB  
VIN3  
„ 256 kHz or 293 kHz chopper clock for Legerity SLIC  
Signal Processing  
Channel 3 (CH 3)  
VOUT3  
devices with switching regulator  
VIN4  
Signal Processing  
Channel 4 (CH 4)  
VOUT4  
„ Maximum channel bandwidth for V.90 modems  
VREF  
SLIC  
Clock  
&
Reference  
Circuits  
CD11  
CD21  
C31  
C41  
FS  
C51  
PCLK  
MCLK/E1  
CD12  
CD22  
C32  
C42  
SLIC  
Interface  
(SLI)  
C52  
RELATED LITERATURE  
„ 080754 Le58QL061/063 QLSLAC™ Device Data Sheet  
CD13  
CD23  
C33  
C43  
C53  
CD14  
CD24  
„ 080761 QSLAC™ to QLSLAC™ Device Design  
C34  
C44  
Conversion Guide  
Microprocessor Interface  
(MPI)  
RST  
C54  
„ 080758 QSLAC™ to QLSLAC™ Guide to New Designs  
CHCLK  
INT  
CS  
DIO  
DCLK  
Microprocessor  
Document ID# 080753 Date:  
May 24, 2006  
Rev:  
F
Version:  
1
Distribution:  
Public Document  
1234567...66

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