Datasheet > LCK4950

LCK4950

更新时间： 2024-09-17 22:28:35

品牌	Logo	应用领域
杰尔 - AGERE		时钟驱动器
页数	文件大小	规格书
16页	205K
描述
Low-Voltage PLL Clock Driver

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LCK4950 数据手册

Data Sheet

November 2001

LCK4950

Low-Voltage PLL Clock Driver

To provide input reference clock flexibility, two

Features

selectable division ratios are available on the

LCK4950. The internal VCO runs at either 2x or 4x

the high-speed output. The FBSEL pin is used to

select between a divide by 8 or a divide by 16 of the

VCO frequency to be compared with the input

reference. These selections allow the input reference

to be either one-half, one-fourth, or one-eighth of the

high-speed output.

■ Fully integrated phase-locked loop (PLL)

■ Oscillator or crystal reference input

■ Output frequency up to 180 MHz

■ Outputs disable in high impedance

■ Compatible with PowerPC^®, Intel^®, and high-

performance RISC microprocessors

The LCK4950 is capable of scan clock distribution or

system diagnostics due to an external test clock

input. The REF_SEL pin allows the selection

between a crystal input to an on-chip oscillator for the

reference or selection of a TTL level oscillator input

directly. Only a parallel resonant crystal is required

for the onboard crystal oscillator external

components.

■ TQFP packaging

■ Output frequency configurable

■ ±35 ps typical cycle-to-cycle jitter

■ Pin compatible with the Motorola^®MPC950 clock

driver

The LCK4950 is fully 3.3 V compatible and requires

no external loop filter components. All inputs accept

LVCMOS or LVTTL compatible levels while the

outputs provide LVCMOS levels with the capability to

drive terminated 50 Ω transmission lines. The

LCK4950 can drive two traces, giving the device an

effective fan out of 1:18 for series-terminated 50 Ω

lines. For optimum performance and board density,

the device is packaged in a 7 mm x 7 mm 32-lead

TQFP package.

Description

The LCK4950 is a PLL-based clock driver device

intended for high-performance clock tree designs.

The LCK4950 is 3.3 V compatible with output

frequencies of up to 180 MHz and output skews of

200 ps. The LCK4950 can accommodate the most

demanding tree designs by employing a fully

differential PLL design. This minimizes cycle-to-cycle

jitter, which is critical when the device is acting as the

reference clock for PLLs in today’s microprocessors

and ASICs. The device has nine low-skew

configurable outputs for support of the clocking

needs of the various high-performance

microprocessors.

12 3 4 5 6 7...16

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