Datasheet > LCK4953

LCK4953

更新时间： 2024-09-17 22:28:35

品牌	Logo	应用领域
杰尔 - AGERE		时钟驱动器逻辑集成电路
页数	文件大小	规格书
6页	97K
描述
Low-Voltage PLL Clock Driver

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LCK4953 数据手册

Data Sheet

November 2001

LCK4953

Low-Voltage PLL Clock Driver

The LCK4953 is fully 3.3 V compatible and requires

no external loop filter components. All control inputs

accept LVCMOS or LVTTL compatible levels while

the outputs provide LVCMOS levels with the ability to

drive terminated 50 Ω transmission lines. For series-

terminated 50 Ω lines, each of the LCK4953 outputs

can drive two traces giving the device an effective

fan-out of 1:18. For the optimum combination of

board density and performance, the device is

Features

• Fully integrated PLL

• Output frequency up to 130 MHz in PLL mode

• Nine outputs with high-impedance disable

• 32-lead TQFP

• 50 ps cycle-to-cycle jitter

packaged in a 7 mm × 7 mm 32-lead TQFP package.

• Pin compatible with the Motorola^®MPC953 clock

driver

Table 1. Function Table

BYPASSB

Function

Description

PLL Enabled

PLL Bypass

The LCK4953 is a PLL-based clock driver device

intended for high-performance clock tree designs.

The LCK4953 is 3.3 V compatible with output

frequencies of up to 130 MHz and output skews of

75 ps. The LCK4953 can meet the most demanding

timing requirements and employs on-chip voltage

regulators to minimize cycle-to-cycle jitter and phase

jitter.

MROEB

Function

Outputs Disabled

Outputs Enabled

VCOSEL

Function

÷ 8

÷ 4

PLLEN

Function

The LCK4953 is ideal for use as a zero delay, low

skew, fan-out buffer due to its differential LVPECL

reference input along with an external feedback

input. The MROEB pin of the LCK4953, when driven

high, will reset the internal counters and 3-state the

output buffers. The LCK4953 has been optimized for

zero delay performance.

Select VCO

Select PELCLK

12 3 4 5 6

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