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L7C197CMB20 PDF预览

L7C197CMB20

更新时间： 2024-02-15 08:32:20
品牌 Logo 应用领域
逻辑 - LOGIC 静态存储器内存集成电路
页数 文件大小 规格书
7页 148K
描述
Standard SRAM, 256KX1, 20ns, CMOS, CDIP24, 0.300 INCH, CERAMIC, DIP-24

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中文翻译

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L7C197CMB20 技术参数

是否Rohs认证：不符合生命周期：Obsolete
零件包装代码：DIP包装说明：DIP, DIP24,.3
针数：24Reach Compliance Code：unknown
ECCN代码：3A001.A.2.CHTS代码：8542.32.00.41
风险等级：5.92Is Samacsys：N
最长访问时间：20 ns其他特性：AUTOMATIC POWER-DOWN; LOW POWER OPERATION; BATTERY BACKUP OPERATION
I/O 类型：SEPARATEJESD-30 代码：R-GDIP-T24
JESD-609代码：e0长度：31.75 mm
内存密度：262144 bit内存集成电路类型：STANDARD SRAM
内存宽度：1湿度敏感等级：3
功能数量：1端口数量：1
端子数量：24字数：262144 words
字数代码：256000工作模式：ASYNCHRONOUS
最高工作温度：125 °C最低工作温度：-55 °C
组织：256KX1输出特性：3-STATE
可输出：NO封装主体材料：CERAMIC, GLASS-SEALED
封装代码：DIP封装等效代码：DIP24,.3
封装形状：RECTANGULAR封装形式：IN-LINE
并行/串行：SERIAL峰值回流温度（摄氏度）：225
电源：5 V认证状态：Not Qualified
筛选级别：38535Q/M;38534H;883B座面最大高度：5.08 mm
最大待机电流：0.0002 A最小待机电流：2 V
子类别：SRAMs最大压摆率：0.125 mA
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：CMOS温度等级：MILITARY
端子面层：Tin/Lead (Sn/Pb)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：7.62 mm
Base Number Matches：1

L7C197CMB20 数据手册

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L7C197  
256K x 1 Static RAM  
DEVICES INCORPORATED  
FEATURES  
DESCRIPTION  
q 256K x 1 Static RAM with Separate  
The L7C197 is a high-performance,  
low-power CMOS static RAM. The  
storage circuitry is organized as  
262,144 words by 1 bit per word. This  
device is available in four speeds with  
maximum access times from 15 ns  
to 35 ns.  
as 2 V. The L7C197 consumes only  
150 µW (typical) at 3 V, allowing  
effective battery backup operation.  
I/O, Chip Select Powerdown  
q Auto-Powerdown™ Design  
q Advanced CMOS Technology  
q High Speed — to 15 ns maximum  
q Low Power Operation  
Active: 165 mW typical at 35 ns  
Standby: 5 mW typical  
q Data Retention at 2 V for Battery  
Backup Operation  
q Available 100% Screened to  
MIL-STD-883, Class B  
q Plug Compatible with IDT71257,  
Cypress CY7C197  
q Package Styles Available:  
• 24-pin Plastic DIP  
The L7C197 provides asynchronous  
(unclocked) operation with matching  
access and cycle times. An active-low  
Chip Enable and a three-state output  
Operation is from a single +5 V power simplify the connection of several  
supply and all interface signals are  
TTL compatible. Power consumption  
is 165 mW (typical) at 35 ns. Dissipa-  
tion drops to 50 mW (typical) when  
the memory is deselected.  
chips for increased capacity.  
Memory locations are specified on ad-  
dress pins A0 through A17. Reading  
from a designated location is accom-  
plished by presenting an address and  
driving CE LOW while WE remains  
HIGH. The data in the addressed  
memory location will then appear on  
the Data Out pin within one access  
time. The output pin stays in a high-  
impedance state when CE is HIGH or  
WE is LOW.  
4
Two standby modes are available.  
Proprietary Auto-Powerdown™  
circuitry reduces power consumption  
automatically during read or write  
accesses which are longer than the  
minimum access time, or when the  
memory is deselected. In addition,  
data may be retained in inactive  
storage with a supply voltage as low  
• 24-pin Ceramic DIP  
• 24-pin Plastic SOJ  
• 28-pin Ceramic LCC  
Writing to an addressed location is  
accomplished when the active-low CE  
and WE inputs are both LOW. Either  
signal may be used to terminate the  
write operation. Data In and Data Out  
signals have the same polarity.  
L7C197 BLOCK DIAGRAM  
D
IN  
Latchup and static discharge pro-  
tection are provided on-chip. The  
L7C197 can withstand an injection  
current of up to 200 mA on any pin  
without damage.  
1024 x 256  
MEMORY  
ARRAY  
10  
ROW  
ADDRESS  
CE  
COLUMN SELECT  
& COLUMN SENSE  
WE  
D
OUT  
8
COLUMN ADDRESS  
256K Static RAMs  
03/05/95–LDS.197-F  
4-3  
1234567

中文翻译

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与L7C197CMB20相关器件

型号 品牌 获取价格 描述 数据表
L7C197CMB25 LOGIC

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 		Standard SRAM, 256KX1, 25ns, CMOS, CDIP24, 0.300 INCH, CERAMIC, DIP-24
L7C197CMB35 LOGIC

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 		Standard SRAM, 256KX1, 35ns, CMOS, CDIP24, 0.300 INCH, CERAMIC, DIP-24
L7C197CMB-45 ETC

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 		x1 SRAM
L7C197CME15 LOGIC

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 		Standard SRAM, 256KX1, 15ns, CMOS, CDIP24, 0.300 INCH, CERDIP-24
L7C197CME-15 ETC

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 		x1 SRAM
L7C197CME20 LOGIC

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 		Standard SRAM, 256KX1, 20ns, CMOS, CDIP24, 0.300 INCH, CERDIP-24
L7C197CME-20 ETC

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 		x1 SRAM
L7C197CME-25 ETC

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 		x1 SRAM
L7C197CME-35 ETC

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 		x1 SRAM
L7C197CME-45 ETC

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 		x1 SRAM

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