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KM62U256CLRG-8L PDF预览

KM62U256CLRG-8L

更新时间: 2024-11-06 11:30:43
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三星 - SAMSUNG /
页数 文件大小 规格书
12页 87K
描述
32Kx8 bit Low Power AND Low Vcc CMOS Static RAM

KM62U256CLRG-8L 数据手册

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KM62V256C, KM62U256C Family  
CMOS SRAM  
32Kx8 bit Low Power & Low Vcc CMOS Static RAM  
FEATURE SUMMARY  
GENERAL DESCRIPTION  
· Process Technology : 0.7µm CMOS  
· Organization : 32K x 8  
The KM62V256C and KM62U256C family are fabricated  
by SAMSUNG's advanced CMOS process technology. The  
family can support various operating temperature ranges  
and has various package types for user flexibility of system  
design. The family also support low data retention voltage  
for battery back-up operation with low data retention  
current.  
· Power Supply Voltage  
KM62V256C family : 3.3V ± 0.3V  
KM62U256C family : 3.0V ± 0.3V  
· Low Data Retention Voltage : 2V(Min)  
· Three state output and TTL Compatible  
· Package Type : JEDEC Standard  
28-SOP, 28-TSOP(I)-Forward/Reverse  
PRODUCT FAMILY  
Power Dissipation  
Speed  
Product  
List  
Operating  
Temp.  
Vcc Range  
PKG Type  
Operating  
(Icc2)  
Standby  
(ns)  
(Isb1, Max)  
KM62V256CL-L  
KM62U256CL-L  
Commercial  
(0~70 °C)  
3.0~3.6V  
2.7~3.3V  
3.0~3.6V  
2.7~3.3V  
3.0~3.6V  
2.7~3.3V  
70*/100  
85*/100  
70*/100  
85*/100  
70*/100  
85*/100  
28-SOP**  
10 µA  
10 µA  
20 µA  
15 µA  
20 µA  
15 µA  
28-TSOP(I) R/F  
28-SOP**  
KM62V256CLE-L Extended  
KM62U256CLE-L (-25~85 °C)  
KM62V256CLI-L Industrial  
KM62U256CLI-L (-40~85 °C)  
* measured with 30pF test load  
35mA  
28-TSOP(I) R/F  
28-SOP**  
28-TSOP(I) R/F  
** the device with 100ns SOP package in 3.0~3.6V Vcc range is not produced.  
PIN DESCRIPTION  
FUNCTIONAL BLOCK DIAGRAM  
A0~2, A9~11  
1
2
3
4
5
6
7
8
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
/OE  
A11  
A9  
A10  
/CS  
IO8  
IO7  
IO6  
IO5  
IO4  
Vss  
IO3  
IO2  
IO1  
A0  
A14  
A12  
A7  
1
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
Vcc  
/WE  
A13  
A8  
Y-Decoder  
2
A8  
3
A13  
/WE  
Vcc  
A14  
A12  
A7  
A6  
A5  
A4  
A3  
A3~A8  
A12~14  
A6  
4
28-Pin TSOP  
Type I - Forward  
A5  
5
A9  
Cell Array  
A4  
6
A11  
/OE  
A10  
/CS  
I/O8  
I/O7  
I/O6  
I/O5  
I/O4  
9
10  
11  
12  
13  
14  
A3  
7
28-Pin SOP  
A2  
8
A1  
A2  
A1  
9
/CS, /WE  
/OE  
A0  
10  
11  
12  
13  
14  
I/O Buffer  
I/O1  
I/O2  
I/O3  
Vss  
I/O1~8  
14  
13  
12  
11  
10  
9
8
7
6
5
A3  
A4  
A5  
A6  
A7  
A12  
A14  
Vcc  
/WE  
A13  
A8  
A9  
A11  
/OE  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
A2  
A1  
A0  
Pin Name Function  
IO1  
IO2  
IO3  
Vss  
IO4  
IO5  
IO6  
IO7  
IO8  
/CS  
A10  
A0~A14  
/WE  
Address Inputs  
Write Enable Input  
Chip Select Input  
Output Enable Input  
Data Input/Output  
Power  
28-Pin TSOP  
Type I - Reverse  
4
3
2
1
/CS  
/OE  
I/O1~I/O8  
Vcc  
Vss  
Ground  
Revision 04  
April 1996  
- 1 -  
ELECTRONICS  

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