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KM416C12CJ-L45 PDF预览

KM416C12CJ-L45

更新时间： 2024-11-07 02:56:35
品牌 Logo 应用领域
三星 - SAMSUNG 存储
页数 文件大小 规格书
35页 804K
描述
1M x 16Bit CMOS Dynamic RAM with Extended Data Out

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KM416C12CJ-L45 数据手册

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KM416C1004C, KM416C1204C  
KM416V1004C, KM416V1204C  
CMOS DRAM  
1M x 16Bit CMOS Dynamic RAM with Extended Data Out  
DESCRIPTION  
This is a family of 1,048,576 x 16 bit Extended Data Out CMOS DRAMs. Extended Data Out Mode offers high speed random access of  
memory cells within the same row, so called Hyper Page Mode. Power supply voltage (+5.0V or +3.3V), refresh cycle (1K Ref. or 4K  
Ref.), access time (-45, -5 or -6), power consumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of  
this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh  
operation is available in L-version. This 1Mx16 EDO Mode DRAM family is fabricated using Samsung¢ s advanced CMOS process to  
realize high band-width, low power consumption and high reliability. It may be used as graphic memory unit for microcomputer, personal  
computer and portable machines.  
FEATURES  
• Part Identification  
• Extended Data Out Mode operation  
(Fast Page Mode with Extended Data Out)  
• 2 CAS Byte/Word Read/Write operation  
- KM416C1004C/C-L (5V, 4K Ref.)  
• CAS-before-RAS refresh capability  
- KM416C1204C/C-L (5V, 1K Ref.)  
• RAS-only and Hidden refresh capability  
• Self-refresh capability (L-ver only)  
- KM416V1004C/C-L (3.3V, 4K Ref.)  
- KM416V1204C/C-L (3.3V, 1K Ref.)  
• TTL(5V)/LVTTL(3.3V) compatible inputs and outputs  
• Early Write or output enable controlled write  
• JEDEC Standard pinout  
• ActivePowerDissipation  
Unit : mW  
5V  
3.3V  
Speed  
• Available in plastic SOJ 400mil and TSOP(II) packages  
• Single +5V±10% power supply (5V product)  
4K  
-
1K  
-
4K  
1K  
-45  
-5  
550  
495  
440  
825  
770  
715  
•
Single +3.3V±0.3V power supply (3.3V product)  
324  
288  
504  
468  
-6  
FUNCTIONAL BLOCK DIAGRAM  
• Refresh Cycles  
Part  
VCC  
Refresh  
cycle  
Refresh period  
RAS  
UCAS  
LCAS  
W
Vcc  
Vss  
NO.  
Control  
Clocks  
Normal  
L-ver  
VBB Generator  
C1004C  
V1004C  
C1204C  
V1204C  
5V  
3.3V  
5V  
4K  
1K  
64ms  
Lower  
Data in  
Buffer  
128ms  
DQ0  
to  
Row Decoder  
Refresh Timer  
Refresh Control  
16ms  
DQ7  
3.3V  
Lower  
Data out  
Buffer  
Memory Array  
1,048,576 x16  
Cells  
OE  
Refresh Counter  
Row Address Buffer  
Col. Address Buffer  
Upper  
Data in  
Buffer  
• Performance Range  
DQ8  
to  
DQ15  
Speed  
-45  
-5  
Remark  
tRAC  
45ns  
50ns  
60ns  
tCAC  
13ns  
15ns  
tRC  
tHPC  
A0-A11  
(A0 - A9)*1  
A0 - A7  
(A0 - A9)*1  
Upper  
Data out  
Buffer  
69ns  
84ns  
16ns 5V/3.3V  
20ns 5V/3.3V  
Column Decoder  
-6  
17ns 104ns 25ns 5V/3.3V  
Note) *1 : 1K Refresh  
SAMSUNG ELECTRONICS CO., LTD. reserves the right to  
change products and specifications without notice.  
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