Datasheet > KBA0401A0M-T401

KBA0401A0M-T401

更新时间： 2024-01-09 20:59:59

品牌	Logo	应用领域
三星 - SAMSUNG		静态存储器内存集成电路
页数	文件大小	规格书
48页	1039K
描述
Memory Circuit, Flash+PSRAM+SRAM, 4MX16, CMOS, PBGA80, 11 X 10 MM, TBGA-80

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KBA0401A0M-T401 技术参数

生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	LFBGA, BGA80,9X12,32	针数：	80
Reach Compliance Code：	compliant	HTS代码：	8542.32.00.71
风险等级：	5.84	最长访问时间：	85 ns
其他特性：	ALSO CONTAINS 2M X 16 UTRAM AND 512K X 16 SRAM	JESD-30 代码：	R-PBGA-B80
长度：	11 mm	内存密度：	67108864 bit
内存集成电路类型：	MEMORY CIRCUIT	内存宽度：	16
混合内存类型：	FLASH+PSRAM+SRAM	功能数量：	1
端子数量：	80	字数：	4194304 words
字数代码：	4000000	工作模式：	ASYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	4MX16	封装主体材料：	PLASTIC/EPOXY
封装代码：	LFBGA	封装等效代码：	BGA80,9X12,32
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY, LOW PROFILE, FINE PITCH
电源：	3 V	认证状态：	Not Qualified
座面最大高度：	1.4 mm	最大待机电流：	0.000006 A
子类别：	Other Memory ICs	最大压摆率：	0.035 mA
最大供电电压 (Vsup)：	3.3 V	最小供电电压 (Vsup)：	2.7 V
标称供电电压 (Vsup)：	3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子形式：	BALL	端子节距：	0.8 mm
端子位置：	BOTTOM	宽度：	10 mm
Base Number Matches：	1

KBA0401A0M-T401 数据手册

TNAL0101

UtRAM USAGE AND TIMING

TECHNICAL

NOTE

UtRAM USAGE AND TIMING

INTRODUCTION

DESIGN ACHIEVES SRAM SPECIFIC

OPERATIONS

The UtRAM was designed to work just like an SRAM - without

any waits or other overhead for precharging or refreshing its

internal DRAM cells. SAMSUNG Electronics(SAMSUNG) hides

these operations inside with advanced design technology -

those are not to be seen from outside. Precharging takes place

during every access, overlapped between the end of the cycle

and the decoding portion of the next cycle.

Hiding refresh is more difficult. Every row in every block must

be refreshed at least once during the refresh interval to prevent

data loss. SAMSUNG provides an internal refresh controller for

devices. When all accesses within refresh interval are directed

to one macro-cell, as can happen in signal processing applica-

tions, a more sophisticated approach is required to hide

refresh. The pseudo SRAM is sometimes used on these appli-

cations, which requires a memory controller that can hold off

accesses when a refresh operation is needed. SAMSUNGs’

unique qualitative advantage over these parts(in addition to

quantitative improvements in access speed and power con-

sumption) is that the UtRAM never need to hold off accesses,

and indeed it has no hold off signal. The circuitry that gives

SAMSUNG this advantage is fairly simple but has not previ-

ously been disclosed.

UtRAM is based on single-transistor DRAM cells. As with any

other DRAM, the data in these cells must be periodically

refreshed to prevent data loss. What makes the UtRAM unique

is that it offers a true SRAM style interface that hides all refresh

operations from the memory controller.

START WITH A DRAM TECHNOLOGY

The key point of UtRAM is its high speed and low power. This

high speed comes from the use of many small blocks such as

32Kbits each to create UtRAM arrays. The small blocks have

short word lines thus with little capacitance eliminating a major

factor of operating current dissipation in conventional DRAM

blocks.

Each independent macro-cell on a UtRAM device consists of a

number of these blocks. Each chip has one or more macro.

The address decoding logic is also fast. UtRAM performs a

complete read operation in every tRC, but UtRAM needs power

up sequence like DRAM.

Power Up Sequence and Diagram

1. Apply power.

2. Maintain stable power for a minium 200ms with CS=high.

3. Issue read operation at least 2 times.

AVOID TIMING

CS=VIL, UB or/and LB=VIL

ZZ=VIH

CS=VIH

Following figures show you an abnormal timing which is not

supported on UtRAM and its solution.

Initial State

(Wait 200ms)

Power On

Active

If your system has a timing which sustains invalid states over

4ms at read mode like Figure 1, there are some guide lines for

proper operation of UtRAM.

Read Operation(2 times)

When your system has multiple invalid address signals shorter

than tRC on the timing shown in Figure 1, UtRAM needs a nor-

mal read timing(tRC) during that cycle(Figure 2) or needs to

toggle CS once to h’ igh’for about t’RC(’Figure 3).

Figure 1.

Over 4ms

Less than tRC

Address

Put on read operation every 4ms

Figure 2.

Over 4ms

tRC

Address

SRAM PRODUCT PLANNING

SAMSUNG Electronics CO., LTD. reserves the right to change products or specifications without notice.

LIM-011025

Ó2002 SAMSUNG Electronics CO., LTD.

- 47 -

1...44 45 464748

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