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K4S561632D-NL75 PDF预览

K4S561632D-NL75

更新时间: 2024-02-03 20:19:57
品牌 Logo 应用领域
三星 - SAMSUNG 时钟动态存储器光电二极管内存集成电路
页数 文件大小 规格书
9页 46K
描述
Synchronous DRAM, 16MX16, 5.4ns, CMOS, PDSO54, 0.300 X 0.551 INCH, 0.50 MM PITCH, STSOP2-54

K4S561632D-NL75 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSOP2包装说明:SOP, TSSOP54,.46,16
针数:54Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.32.00.24
风险等级:5.75访问模式:FOUR BANK PAGE BURST
最长访问时间:5.4 ns其他特性:AUTO/SELF REFRESH
最大时钟频率 (fCLK):133 MHzI/O 类型:COMMON
交错的突发长度:1,2,4,8JESD-30 代码:R-PDSO-G54
JESD-609代码:e0内存密度:268435456 bit
内存集成电路类型:SYNCHRONOUS DRAM内存宽度:16
功能数量:1端口数量:1
端子数量:54字数:16777216 words
字数代码:16000000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:16MX16输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:TSSOP54,.46,16封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):240
电源:3.3 V认证状态:Not Qualified
刷新周期:8192自我刷新:YES
连续突发长度:1,2,4,8,FP最大待机电流:0.002 A
子类别:DRAMs最大压摆率:0.2 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.4 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30Base Number Matches:1

K4S561632D-NL75 数据手册

 浏览型号K4S561632D-NL75的Datasheet PDF文件第3页浏览型号K4S561632D-NL75的Datasheet PDF文件第4页浏览型号K4S561632D-NL75的Datasheet PDF文件第5页浏览型号K4S561632D-NL75的Datasheet PDF文件第7页浏览型号K4S561632D-NL75的Datasheet PDF文件第8页浏览型号K4S561632D-NL75的Datasheet PDF文件第9页 
K4S561632D  
CMOS SDRAM  
DC CHARACTERISTICS  
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)  
Version  
Parameter  
Symbol  
Test Condition  
Unit Note  
-60  
-7C  
-75  
-1H -1L  
Burst length = 1  
tRC ³ tRC(min)  
IO = 0 mA  
Operating current  
(One bank active)  
ICC1  
150 110  
100  
100 100  
mA  
mA  
1
ICC2P  
CKE £ VIL(max), tCC = 10ns  
2
2
Precharge standby cur-  
rent in power-down mode  
ICC2PS  
CKE & CLK £ VIL(max), tCC = ¥  
CKE ³ VIH(min), CS ³ VIH(min), tCC = 10ns  
ICC2N  
20  
10  
Precharge standby cur-  
rent in non power-down  
mode  
Input signals are changed one time during 20ns  
mA  
CKE ³ VIH(min), CLK £ VIL(max), tCC = ¥  
Input signals are stable  
ICC2NS  
ICC3P  
6
6
CKE £ VIL(max), tCC = 10ns  
Active standby current in  
power-down mode  
mA  
mA  
mA  
ICC3PS  
CKE & CLK £ VIL(max), tCC = ¥  
CKE ³ VIH(min), CS ³ VIH(min), tCC = 10ns  
Input signals are changed one time during 20ns  
ICC3N  
30  
25  
Active standby current in  
non power-down mode  
(One bank active)  
CKE ³ VIH(min), CLK £ VIL(max), tCC = ¥  
Input signals are stable  
ICC3NS  
IO = 0 mA  
Operating current  
(Burst mode)  
Page burst  
ICC4  
180 140  
220 220  
140  
130 130  
190 190  
mA  
1
4banks Activated.  
tCCD = 2CLKs  
Refresh current  
ICC5  
ICC6  
tRC ³ tRC(min)  
200  
3
mA  
mA  
mA  
2
3
4
C
Self refresh current  
CKE £ 0.2V  
L
1.5  
Notes :  
1. Measured with outputs open.  
2. Refresh period is 64ms.  
3. K4S561632D-NC**  
4. K4S561632D-NL**  
5. Unless otherwise noticed, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ).  
Rev. 0.1 Aug. 2002  

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