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K4F641612D-TL500 PDF预览

K4F641612D-TL500

更新时间: 2024-11-11 13:59:31
品牌 Logo 应用领域
三星 - SAMSUNG 动态存储器光电二极管内存集成电路
页数 文件大小 规格书
35页 846K
描述
Fast Page DRAM, 4MX16, 50ns, CMOS, PDSO50, 0.400 INCH, PLASTIC, TSOP2-50

K4F641612D-TL500 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:TSOP2包装说明:TSOP2,
针数:50Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.32.00.02
风险等级:5.5Is Samacsys:N
访问模式:FAST PAGE最长访问时间:50 ns
其他特性:RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESH/SELF REFRESHJESD-30 代码:R-PDSO-G50
长度:20.95 mm内存密度:67108864 bit
内存集成电路类型:FAST PAGE DRAM内存宽度:16
功能数量:1端口数量:1
端子数量:50字数:4194304 words
字数代码:4000000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:4MX16封装主体材料:PLASTIC/EPOXY
封装代码:TSOP2封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE峰值回流温度(摄氏度):240
认证状态:Not Qualified座面最大高度:1.2 mm
自我刷新:YES最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:0.8 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:10.16 mm
Base Number Matches:1

K4F641612D-TL500 数据手册

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K4F661612D,K4F641612D  
CMOS DRAM  
4M x 16bit CMOS Dynamic RAM with Fast Page Mode  
DESCRIPTION  
This is a family of 4,194,304 x 16 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory  
cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-45, -50 or -60), power consumption(Normal or Low power)  
are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities.  
Furthermore, Self-refresh operation is available in L-version. This 4Mx16 Fast Page Mode DRAM family is fabricated using Samsung¢s  
advanced CMOS process to realize high band-width, low power consumption and high reliability.  
FEATURES  
• Fast Page Mode operation  
• Part Identification  
• 2CAS Byte/Word Read/Write operation  
• CAS-before-RAS refresh capability  
• RAS-only and Hidden refresh capability  
• Self-refresh capability (L-ver only)  
• Fast parallel test mode capability  
• LVTTL(3.3V) compatible inputs and outputs  
• Early Write or output enable controlled write  
• JEDEC Standard pinout  
- K4F661612D-TC/L(3.3V, 8K Ref.)  
- K4F641612D-TC/L(3.3V, 4K Ref.)  
ActivePowerDissipation  
Unit : mW  
Speed  
-45  
8K  
4K  
468  
432  
396  
• Available in Plastic TSOP(II) packages  
• +3.3V±0.3V power supply  
324  
288  
252  
-50  
-60  
Refresh Cycles  
Part  
NO.  
Refresh  
cycle  
Refresh time  
FUNCTIONAL BLOCK DIAGRAM  
Normal  
L-ver  
K4F661612D*  
K4F641612D  
8K  
4K  
RAS  
UCAS  
LCAS  
W
64ms  
128ms  
Vcc  
Vss  
Control  
Clocks  
VBB Generator  
* Access mode & RAS only refresh mode  
Lower  
Data in  
Buffer  
: 8K cycle/64ms(Normal), 8K cycle/128ms(L-ver.)  
CAS-before-RAS & Hidden refresh mode  
DQ0  
to  
Row Decoder  
Refresh Timer  
DQ7  
Lower  
Data out  
Buffer  
: 4K cycle/64ms(Normal), 4K cycle/128ms(L-ver.)  
Refresh Control  
Memory Array  
OE  
4,194,304 x 16  
Cells  
Refresh Counter  
Row Address Buffer  
Col. Address Buffer  
Upper  
Data in  
Buffer  
Performance Range  
DQ8  
to  
DQ15  
Speed  
tRAC  
45ns  
50ns  
60ns  
tCAC  
12ns  
13ns  
15ns  
tRC  
tPC  
A0~A12  
(A0~A11)*1  
Upper  
Data out  
Buffer  
-45  
-50  
-60  
80ns  
90ns  
110ns  
31ns  
35ns  
40ns  
A0~A8  
(A0~A9)*1  
Column Decoder  
Note) *1 : 4K Refresh  
SAMSUNG ELECTRONICS CO., LTD. reserves the right to  
change products and specifications without notice.  

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