Datasheet > K4F151612D-J50

K4F151612D-J50

更新时间： 2024-01-17 02:16:16

品牌	Logo	应用领域
三星 - SAMSUNG		动态存储器
页数	文件大小	规格书
34页	352K
描述
DRAM

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K4F151612D-J50 数据手册

K4F171611D, K4F151611D

K4F171612D, K4F151612D

CMOS DRAM

1M x 16Bit CMOS Dynamic RAM with Fast Page Mode

DESCRIPTION

This is a family of 1,048,576 x 16 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory

cells within the same row. Power supply voltage (+5.0V or +3.3V), refresh cycle (1K Ref. or 4K Ref.), access time (-50 or -60), power

consumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of this family. All of this family have CAS-

before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This

1Mx16 Fast Page Mode DRAM family is fabricated using Samsung¢s advanced CMOS process to realize high band-width, low power

consumption and high reliability. It may be used as graphic memory unit for microcomputer, personal computer and portable machines.

FEATURES

• Fast Page Mode operation

• Part Identification

• 2 CAS Byte/Word Read/Write operation

• CAS-before-RAS refresh capability

- K4F171611D-J(T) (5V, 4K Ref.)

- K4F151611D-J(T) (5V, 1K Ref.)

- K4F171612D-J(T) (3.3V, 4K Ref.)

- K4F151612D-J(T) (3.3V, 1K Ref.)

• RAS-only and Hidden refresh capability

• Self-refresh capability (L-ver only)

• TTL(5V)/LVTTL(3.3V) compatible inputs and outputs

• Early Write or output enable controlled write

• JEDEC Standard pinout

• Active Power Dissipation

Unit : mW

• Available in 42-pin SOJ 400mil and 50(44)-pin TSOP(II)

3.3V

400mil packages

• Single +5V±10% power supply (5V product)

Speed

324

288

770

715

• Single +3.3V±0.3V power supply (3.3V product)

-50

-60

504

468

495

440

FUNCTIONAL BLOCK DIAGRAM

• Refresh Cycles

Part

NO.

Refresh

cycle

Refresh period

Normal L-ver

VCC

RAS

UCAS

LCAS

Vcc

Vss

Control

Clocks

VBB Generator

K4F171611D

64ms

128ms

16ms

Lower

K4F171612D 3.3V

K4F151611D 5V

Data in

DQ0

Refresh Timer

Refresh Control

Row Decoder

Buffer

DQ7

K4F151612D 3.3V

Lower

Data out

Buffer

Memory Array

1,048,576 x16

Cells

Refresh Counter

Row Address Buffer

Col. Address Buffer

Upper

Data in

Buffer

• Perfomance Range

A0-A11

(A0 - A9)*1

A0 - A7

DQ8

DQ15

Speed

-50

Remark

35ns 5V/3.3V

tRAC

50ns

60ns

tCAC

tRC

tPC

Upper

Data out

Buffer

15ns

90ns

Column Decoder

(A0 - A9)*1

-60

15ns 110ns 40ns 5V/3.3V

Note) *1 : 1K Refresh

SAMSUNG ELECTRONICS CO., LTD. reserves the right to

change products and specifications without notice.

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