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4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory
General Description
General Description
Micron NAND Flash devices include an asynchronous data interface for high-perform-
ance I/O operations. These devices use a highly multiplexed 8-bit bus (I/Ox) to transfer
commands, address, and data. There are five control signals used to implement the
asynchronous data interface: CE#, CLE, ALE, WE#, and RE#. Additional signals control
hardware write protection and monitor device status (R/B#).
This hardware interface creates a low pin-count device with a standard pinout that re-
mains the same from one density to another, enabling future upgrades to higher densi-
ties with no board redesign.
A target is the unit of memory accessed by a chip enable signal. A target contains one or
more NAND Flash die. A NAND Flash die is the minimum unit that can independently
execute commands and report status. A NAND Flash die, in the ONFI specification, is
referred to as a logical unit (LUN). There is at least one NAND Flash die per chip enable
signal. For further details, see Device and Array Organization.
This device has an internal 4-bit ECC that can be enabled using the GET/SET features.
See Internal ECC and Spare Area Mapping for ECC for more information.
Signal Descriptions
Table 1: Signal Definitions
Signal1
Type
Input
Input
Description2
ALE
Address latch enable: Loads an address from I/O[7:0] into the address register.
CE#
CE#2
Chip enable: Enables or disables one or more die (LUNs) in a target.
For the 16Gb device, CE# controls the first 8Gb of memory; CE2# controls the second 8Gb
of memory.
CLE
Input
Input
Command latch enable: Loads a command from I/O[7:0] into the command register.
LOCK
When LOCK is HIGH during power-up, the BLOCK LOCK function is enabled. To disable the
BLOCK LOCK, connect LOCK to VSS during power-up, or leave it disconnected (internal
pull-down).
RE#
Input
Input
Read enable: Transfers serial data from the NAND Flash to the host system.
WE#
Write enable: Transfers commands, addresses, and serial data from the host system to the
NAND Flash.
WP#
Input
I/O
Write protect: Enables or disables array PROGRAM and ERASE operations.
I/O[7:0] (x8)
Data inputs/outputs: The bidirectional I/Os transfer address, data, and command infor-
I/O[15:0] (x16)
mation.
R/B#
R/B#2
Output
Ready/busy: An open-drain, active-low output that requires an external pull-up resistor.
This signal indicates target array activity.
For the 16Gb device, R/B# indicates the status of the first 8Gb of memory; R/B# indicates
the status of the second 8Gb of memory.
VCC
VSS
Supply
VCC: Core power supply
Supply
VSS: Core ground connection
NC
–
–
No connect: NCs are not internally connected. They can be driven or left unconnected.
Do not use: DNUs must be left unconnected.
DNU
1. See Device and Array Organization for detailed signal connections.
Notes:
PDF: 09005aef83b25735
m60a_4gb_8gb_16gb_ecc_nand.pdf - Rev. N 10/12 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
8
© 2009 Micron Technology, Inc. All rights reserved.
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