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JM38510/65308BEA PDF预览

JM38510/65308BEA

更新时间: 2024-11-20 02:50:39
品牌 Logo 应用领域
德州仪器 - TI 触发器锁存器逻辑集成电路
页数 文件大小 规格书
16页 583K
描述
QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR

JM38510/65308BEA 技术参数

生命周期:Active零件包装代码:DIP
包装说明:DIP,针数:16
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
Factory Lead Time:6 weeks风险等级:5.08
系列:HC/UHJESD-30 代码:R-GDIP-T16
长度:19.56 mm负载电容(CL):50 pF
逻辑集成电路类型:D FLIP-FLOP最大频率@ Nom-Sup:21000000 Hz
最大I(ol):0.0052 A位数:4
功能数量:1端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
输出极性:COMPLEMENTARY封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE包装方法:TUBE
峰值回流温度(摄氏度):NOT SPECIFIED最大电源电流(ICC):0.08 mA
Prop。Delay @ Nom-Sup:45 ns传播延迟(tpd):255 ns
认证状态:Not Qualified筛选级别:MIL-M-38510 Class B
座面最大高度:5.08 mm最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:6.92 mm最小 fmax:25 MHz
Base Number Matches:1

JM38510/65308BEA 数据手册

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ꢀꢁꢂ ꢃ ꢄꢅ ꢆ ꢇꢂ ꢈ ꢀꢁꢇ ꢃꢄ ꢅꢆ ꢇꢂ  
ꢉ ꢊꢋꢌꢍ ꢊꢎꢏ ꢐ ꢌꢑꢒ ꢓꢎ ꢐ ꢔ ꢏ ꢕꢎ ꢑ ꢔꢏꢖ ꢎ ꢀ  
ꢗ ꢕꢒꢄ ꢅ ꢏꢐ ꢋꢍ  
SCLS299D − JANUARY 1996 − REVISED SEPTEMBER 2003  
D
D
D
D
Wide Operating Voltage Range of 2 V to 6 V  
Outputs Can Drive Up To 10 LSTTL Loads  
D
D
D
4-mA Output Drive at 5 V  
Low Input Current of 1 µA Max  
Low Power Consumption, 80-µA Max I  
Applications Include:  
− Buffer/Storage Registers  
− Shift Registers  
CC  
Contain Four Flip-Flops With Double-Rail  
Outputs  
− Pattern Generators  
D
Typical t = 13 ns  
pd  
SN54HC175 . . . FK PACKAGE  
(TOP VIEW)  
SN54HC175 . . . J OR W PACKAGE  
SN74HC175 . . . D, DB, N, NS, OR PW PACKAGE  
(TOP VIEW)  
CLR  
1Q  
1Q  
1D  
2D  
2Q  
2Q  
GND  
V
CC  
4Q  
1
2
3
4
5
6
7
8
16  
15  
3
2
1
20 19  
18  
4Q  
4D  
NC  
1Q  
1D  
NC  
2D  
2Q  
4
5
6
7
8
14 4Q  
13 4D  
12 3D  
11 3Q  
17  
16  
15 3D  
14  
3Q  
9 10 11 12 13  
10  
9
3Q  
CLK  
NC − No internal connection  
description/ordering information  
These positive-edge-triggered D-type flip-flops have a direct clear (CLR) input. The ’HC175 devices feature  
complementary outputs from each flip-flop.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
PDIP − N  
SOIC − D  
Tube of 25  
Tube of 40  
Reel of 2500  
Reel of 250  
Reel of 2000  
Reel of 2000  
Tube of 90  
Reel of 2000  
Reel of 250  
Tube of 25  
Tube of 150  
Tube of 55  
SN74HC175N  
SN74HC175N  
SN74HC175D  
SN74HC175DR  
SN74HC175DT  
SN74HC175NSR  
SN74HC175DBR  
SN74HC175PW  
SN74HC175PWR  
SN74HC175PWT  
SNJ54HC175J  
SNJ54HC175W  
SNJ54HC175FK  
HC175  
SOP − NS  
HC175  
HC175  
−40°C to 85°C  
SSOP − DB  
TSSOP − PW  
HC175  
CDIP − J  
CFP − W  
LCCC − FK  
SNJ54HC175J  
SNJ54HC175W  
SNJ54HC175FK  
−55°C to 125°C  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
ꢖ ꢙ ꢤ ꢜ ꢛꢧ ꢢꢡ ꢟꢠ ꢡꢛ ꢝꢤ ꢦꢘ ꢞꢙ ꢟ ꢟꢛ ꢮꢕ ꢏꢑ ꢎꢍ ꢔ ꢑꢯꢰꢂ ꢯꢂꢈ ꢞꢦꢦ ꢤꢞ ꢜ ꢞ ꢝꢣ ꢟꢣꢜ ꢠ ꢞ ꢜ ꢣ ꢟꢣ ꢠꢟꢣ ꢧ  
ꢟ ꢣ ꢠ ꢟꢘ ꢙꢭ ꢛꢚ ꢞ ꢦꢦ ꢤꢞ ꢜ ꢞ ꢝ ꢣ ꢟ ꢣ ꢜ ꢠ ꢨ  
ꢢ ꢙꢦ ꢣꢠꢠ ꢛ ꢟꢩꢣ ꢜ ꢫꢘ ꢠꢣ ꢙ ꢛꢟꢣ ꢧꢨ ꢖ ꢙ ꢞꢦ ꢦ ꢛ ꢟꢩꢣ ꢜ ꢤꢜ ꢛ ꢧꢢꢡ ꢟꢠ ꢈ ꢤꢜ ꢛ ꢧꢢꢡ ꢟꢘꢛ ꢙ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

JM38510/65308BEA 替代型号

型号 品牌 替代类型 描述 数据表
SN54LS375J TI

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SN74LS375N TI

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4-BIT BISTABLE LATCHES

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