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JM38510/65704BRA PDF预览

JM38510/65704BRA

更新时间: 2024-11-20 05:27:51
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器逻辑集成电路输出元件
页数 文件大小 规格书
14页 434K
描述
OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS

JM38510/65704BRA 技术参数

生命周期:Active零件包装代码:DIP
包装说明:DIP-20针数:20
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:5.14Is Samacsys:N
控制类型:ENABLE LOW/HIGH系列:HC/UH
JESD-30 代码:R-GDIP-T20长度:24.2 mm
负载电容(CL):150 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.006 A位数:4
功能数量:2端口数量:2
端子数量:20最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE包装方法:TUBE
峰值回流温度(摄氏度):NOT SPECIFIED最大电源电流(ICC):0.16 mA
Prop。Delay @ Nom-Sup:34 ns传播延迟(tpd):245 ns
认证状态:Not Qualified筛选级别:MIL-M-38510 Class B
座面最大高度:5.08 mm最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:6.92 mm
Base Number Matches:1

JM38510/65704BRA 数据手册

 浏览型号JM38510/65704BRA的Datasheet PDF文件第2页浏览型号JM38510/65704BRA的Datasheet PDF文件第3页浏览型号JM38510/65704BRA的Datasheet PDF文件第4页浏览型号JM38510/65704BRA的Datasheet PDF文件第5页浏览型号JM38510/65704BRA的Datasheet PDF文件第6页浏览型号JM38510/65704BRA的Datasheet PDF文件第7页 
ꢊ ꢅꢋꢌꢍ ꢎꢏꢐ ꢐ ꢑꢒꢀ ꢌꢁꢓ ꢍ ꢔꢁꢑ ꢓ ꢒꢔ ꢕ ꢑꢒ  
SCLS300C − JANUARY 1996 − REVISED AUGUST 2003  
D
D
Wide Operating Voltage Range of 2 V to 6 V  
D
D
D
6-mA Output Drive at 5 V  
High-Current Outputs Drive Up To 15  
LSTTL Loads  
Low Input Current of 1 µA Max  
3-State Outputs Drive Bus Lines or Buffer  
Memory Address Registers  
D
Low Power Consumption, 80-µA Max I  
CC  
D
Typical t = 11 ns  
pd  
SN54HC241 . . . J OR W PACKAGE  
SN74HC241 . . . DW, N, NS, OR PW PACKAGE  
(TOP VIEW)  
SN54HC241 . . . FK PACKAGE  
(TOP VIEW)  
1OE  
1A1  
2Y4  
1A2  
2Y3  
1A3  
2Y2  
1A4  
2Y1  
GND  
V
CC  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
2OE  
1Y1  
2A4  
1Y2  
2A3  
1Y3  
2A2  
1Y4  
2A1  
3
2
1
20 19  
18  
1A2  
2Y3  
1A3  
2Y2  
1A4  
1Y1  
2A4  
1Y2  
2A3  
4
5
6
7
8
17  
16  
15  
14 1Y3  
9 10 11 12 13  
description/ordering information  
These octal buffers and line drivers are designed specifically to improve both the performance and density of  
3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The ’HC241  
devices are organized as two 4-bit buffers/drivers with separate output-enable (1OE and 2OE) inputs. When  
1OE is low or 2OE is high, the device passes noninverted data from the A inputs to the Y outputs. When 1OE  
is high or 2OE is low, the outputs for the respective buffers/drivers are in the high-impedance state.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
PDIP − N  
Tube of 20  
Tube of 25  
Reel of 2000  
Reel of 2000  
Reel of 70  
SN74HC241N  
SN74HC241N  
SN74HC241DW  
SN74HC241DWR  
SN74HC241NSR  
SN74HC241PW  
SN74HC241PWR  
SN74HC241PWT  
SNJ54HC241J  
SOIC − DW  
SOP − NS  
HC241  
HC241  
−40°C to 85°C  
Reel of 2000  
Reel of 250  
Tube of 20  
Tube of 85  
Tube of 55  
TSSOP − PW  
HC241  
CDIP − J  
CFP − W  
LCCC − FK  
SNJ54HC241J  
SNJ54HC241W  
SNJ54HC241FK  
SNJ54HC241W  
SNJ54HC241FK  
−55°C to 125°C  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
ꢊ ꢛ ꢦ ꢞ ꢝꢩ ꢤꢣ ꢡꢢ ꢣꢝ ꢟꢦ ꢨꢚ ꢠꢛ ꢡ ꢡꢝ ꢰꢔ ꢍꢘ ꢙꢒ ꢐ ꢘꢗꢱꢂ ꢗꢂꢈ ꢠꢨꢨ ꢦꢠ ꢞ ꢠ ꢟꢥ ꢡꢥꢞ ꢢ ꢠ ꢞ ꢥ ꢡꢥ ꢢꢡꢥ ꢩ  
ꢡ ꢥ ꢢ ꢡꢚ ꢛꢯ ꢝꢜ ꢠ ꢨꢨ ꢦꢠ ꢞ ꢠ ꢟ ꢥ ꢡ ꢥ ꢞ ꢢ ꢪ  
ꢤ ꢛꢨ ꢥꢢꢢ ꢝ ꢡꢫꢥ ꢞ ꢭꢚ ꢢꢥ ꢛ ꢝꢡꢥ ꢩꢪ ꢊ ꢛ ꢠꢨ ꢨ ꢝ ꢡꢫꢥ ꢞ ꢦꢞ ꢝ ꢩꢤꢣ ꢡꢢ ꢈ ꢦꢞ ꢝ ꢩꢤꢣ ꢡꢚꢝ ꢛ  
ꢛꢯ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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