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JL82576EB/SLJBH PDF预览

JL82576EB/SLJBH

更新时间: 2024-10-28 21:05:31
品牌 Logo 应用领域
英特尔 - INTEL 通信时钟局域网PC外围集成电路
页数 文件大小 规格书
956页 7088K
描述
2 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PBGA576, 25 X 25 MM, 1 MM PITCH, FCBGA-576

JL82576EB/SLJBH 技术参数

是否Rohs认证: 符合生命周期:Lifetime Buy
零件包装代码:BGA包装说明:25 X 25 MM, 1 MM PITCH, FCBGA-576
针数:576Reach Compliance Code:compliant
风险等级:5.75地址总线宽度:
边界扫描:YES总线兼容性:PCI
最大时钟频率:25 MHz通信协议:ASYNC, BIT; I2C
外部数据总线宽度:JESD-30 代码:S-PBGA-B576
长度:25 mm低功率模式:YES
串行 I/O 数:2端子数量:576
最高工作温度:55 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装等效代码:BGA576,24X24,40封装形状:SQUARE
封装形式:GRID ARRAY电源:1,1.8,3.3 V
认证状态:Not Qualified子类别:Serial IO/Communication Controllers
标称供电电压:1 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM宽度:25 mm
uPs/uCs/外围集成电路类型:SERIAL IO/COMMUNICATION CONTROLLER, LANBase Number Matches:1

JL82576EB/SLJBH 数据手册

 浏览型号JL82576EB/SLJBH的Datasheet PDF文件第6页浏览型号JL82576EB/SLJBH的Datasheet PDF文件第7页浏览型号JL82576EB/SLJBH的Datasheet PDF文件第8页浏览型号JL82576EB/SLJBH的Datasheet PDF文件第10页浏览型号JL82576EB/SLJBH的Datasheet PDF文件第11页浏览型号JL82576EB/SLJBH的Datasheet PDF文件第12页 
Contents — Intel® 82576EB GbE Controller  
2.1.9  
Testability Pins ................................................................................................................... 66  
2.1.10  
2.1.11  
2.2  
2.3  
2.4  
2.5  
2.6  
Reserved Pins and No-Connects ............................................................................................ 66  
Power Supply Pins............................................................................................................... 68  
Pull-ups/Pull-downs ................................................................................................................... 68  
Strapping ................................................................................................................................. 71  
Interface Diagram ..................................................................................................................... 72  
Pin List (Alphabetical) ................................................................................................................ 73  
Ball Out.................................................................................................................................... 75  
3.0  
Interconnects............................................................................................................................ 77  
3.1  
PCIe ........................................................................................................................................ 77  
3.1.1  
PCIe Overview .................................................................................................................... 77  
Architecture, Transaction and Link Layer Properties ........................................................... 78  
Physical Interface Properties........................................................................................... 79  
Advanced Extensions..................................................................................................... 79  
Functionality - General......................................................................................................... 79  
Native/Legacy .............................................................................................................. 79  
Locked Transactions...................................................................................................... 79  
End to End CRC (ECRC) ................................................................................................. 79  
Host I/F ............................................................................................................................. 80  
Tag IDs ....................................................................................................................... 80  
3.1.1.1  
3.1.1.2  
3.1.1.3  
3.1.2  
3.1.2.1  
3.1.2.2  
3.1.2.3  
3.1.3  
3.1.3.1  
3.1.3.1.1  
3.1.3.1.2  
TAG ID Allocation for Read Transactions........................................................................ 80  
TAG ID Allocation for Write Transactions ....................................................................... 80  
Case 1 - DCA Disabled in the System:.................................................................... 81  
Case 2 - DCA Enabled in the System, but Disabled for the Request: ........................... 81  
Case 3 - DCA Enabled in the System, DCA Enabled for the Request:........................... 81  
3.1.3.1.2.1  
3.1.3.1.2.2  
3.1.3.1.2.3  
3.1.3.2  
3.1.3.2.1  
3.1.3.2.2  
3.1.3.2.3  
Completion Timeout Mechanism...................................................................................... 81  
Completion Timeout Enable......................................................................................... 82  
Resend Request Enable............................................................................................... 82  
Completion Timeout Period.......................................................................................... 83  
3.1.4  
3.1.4.1  
3.1.4.1.1  
3.1.4.1.2  
3.1.4.2  
3.1.4.2.1  
3.1.4.2.2  
3.1.4.3  
3.1.4.3.1  
3.1.4.3.2  
3.1.4.4  
3.1.4.4.1  
3.1.4.5  
Transaction Layer................................................................................................................ 84  
Transaction Types Accepted by the 82576........................................................................ 84  
Configuration Request Retry Status.............................................................................. 85  
Partial Memory Read and Write Requests ...................................................................... 85  
Transaction Types Initiated by the 82576......................................................................... 85  
Data Alignment.......................................................................................................... 85  
Multiple Tx Data Read Requests................................................................................... 86  
Messages..................................................................................................................... 86  
Message Handling by the 82576 (as a Receiver)............................................................. 86  
Message Handling by the 82576 (as a Transmitter) ........................................................ 87  
Ordering Rules ............................................................................................................. 87  
Out of Order Completion Handling................................................................................ 88  
Transaction Definition and Attributes ............................................................................... 88  
Max Payload Size....................................................................................................... 88  
Traffic Class (TC) and Virtual Channels (VC) .................................................................. 88  
Relaxed Ordering....................................................................................................... 88  
Snoop Not Required ................................................................................................... 89  
No Snoop and Relaxed Ordering for LAN Traffic.............................................................. 89  
3.1.4.5.1  
3.1.4.5.2  
3.1.4.5.3  
3.1.4.5.4  
3.1.4.5.5  
3.1.4.5.5.1  
3.1.4.5.5.2  
No-Snoop Option for Payload ................................................................................ 90  
No Snoop Option for TSO Header........................................................................... 90  
3.1.4.6  
3.1.4.6.1  
3.1.4.6.2  
3.1.4.6.3  
3.1.4.6.4  
Flow Control................................................................................................................. 90  
82576 Flow Control Rules............................................................................................ 90  
Upstream Flow Control Tracking................................................................................... 91  
Flow Control Update Frequency.................................................................................... 91  
Flow Control Timeout Mechanism ................................................................................. 91  
Error Forwarding........................................................................................................... 91  
3.1.4.7  
3.1.5  
3.1.5.1  
3.1.5.2  
3.1.5.3  
Data Link Layer................................................................................................................... 91  
ACK/NAK Scheme ......................................................................................................... 91  
Supported DLLPs .......................................................................................................... 92  
Transmit EDB Nullifying ................................................................................................. 93  
Physical Layer..................................................................................................................... 93  
3.1.6  
Revision: 2.63  
December 2011  
Intel® 82576EB GbE Controller  
Datasheet  
9

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