Intel® 82576EB GbE Controller — Contents
3.1.6.1
3.1.6.2
3.1.6.3
3.1.6.4
3.1.6.5
3.1.6.6
3.1.6.7
Link Width ................................................................................................................... 93
Polarity Inversion.......................................................................................................... 93
L0s Exit latency ............................................................................................................ 93
Lane-to-Lane De-Skew .................................................................................................. 93
Lane Reversal............................................................................................................... 94
Reset .......................................................................................................................... 94
Scrambler Disable......................................................................................................... 95
Error Events and Error Reporting........................................................................................... 95
Mechanism in General.................................................................................................... 95
Error Events................................................................................................................. 96
Error Pollution .............................................................................................................. 98
Completion with Unsuccessful Completion Status............................................................... 98
Error Reporting Changes................................................................................................ 98
Performance Monitoring ....................................................................................................... 99
Leaky Bucket Mode ....................................................................................................... 99
PCIe Power Management.................................................................................................... 100
PCIe Programming Interface............................................................................................... 100
Management Interfaces............................................................................................................ 100
SMBus ............................................................................................................................. 100
3.1.7
3.1.7.1
3.1.7.2
3.1.7.3
3.1.7.4
3.1.7.5
3.1.8
3.1.8.1
3.1.9
3.1.10
3.2
3.2.1
3.2.1.1
3.2.1.1.1
3.2.1.1.2
Channel Behavior.........................................................................................................100
SMBus Addressing.....................................................................................................100
SMBus Notification Methods........................................................................................101
3.2.1.1.2.1
3.2.1.1.2.2
3.2.1.1.2.3
3.2.1.1.3
3.2.1.1.4
3.2.1.1.5
3.2.1.1.6
3.2.1.1.7
3.2.1.1.8
3.2.1.1.8.1
3.2.1.1.8.2
3.2.1.1.8.3
3.2.1.1.9
SMBus Alert and Alert Response Method ................................................................101
Asynchronous Notify Method ................................................................................102
Direct Receive Method.........................................................................................103
Receive TCO Flow .....................................................................................................103
Transmit TCO Flow....................................................................................................104
Transmit Errors in Sequence Handling..........................................................................104
TCO Command Aborted Flow ......................................................................................105
Concurrent SMBus Transactions ..................................................................................105
SMBus ARP Functionality............................................................................................105
SMBus ARP in Dual-/Single-Address Mode..............................................................106
SMBus ARP Flow.................................................................................................106
SMBus ARP UDID Content....................................................................................107
LAN Fail-Over Through SMBus ....................................................................................109
3.2.2
3.2.2.1
3.2.2.2
NC-SI .............................................................................................................................. 109
Electrical Characteristics ...............................................................................................109
NC-SI Transactions ......................................................................................................110
3.3
3.3.1
3.3.1.1
3.3.1.2
Flash / EEPROM....................................................................................................................... 110
EEPROM Interface ............................................................................................................. 110
General Overview.........................................................................................................110
EEPROM Device ...........................................................................................................111
Software Accesses .......................................................................................................111
Signature Field ............................................................................................................112
Protected EEPROM Space ..............................................................................................112
Initial EEPROM Programming ......................................................................................112
Activating the Protection Mechanism............................................................................112
Non Permitted Accessing to Protected Areas in the EEPROM............................................112
EEPROM Recovery........................................................................................................113
EEPROM-Less Support ..................................................................................................113
Access to the EEPROM Controlled Feature.....................................................................114
3.3.1.3
3.3.1.4
3.3.1.5
3.3.1.5.1
3.3.1.5.2
3.3.1.5.3
3.3.1.6
3.3.1.7
3.3.1.7.1
3.3.2
3.3.2.1
3.3.2.2
3.3.3
3.3.4
3.3.4.1
3.3.4.2
3.3.4.3
Shared EEPROM ................................................................................................................ 115
EEPROM Deadlock Avoidance.........................................................................................115
EEPROM Map Shared Words ..........................................................................................115
Vital Product Data (VPD) Support ........................................................................................ 116
Flash Interface.................................................................................................................. 117
Flash Interface Operation..............................................................................................117
Flash Write Control.......................................................................................................118
Flash Erase Control ......................................................................................................118
Shared FLASH................................................................................................................... 119
Flash Access Contention................................................................................................119
3.3.5
3.3.5.1
Intel® 82576EB GbE Controller
Datasheet
10
Revision: 2.63
December 2011
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