Datasheet > ISPLSI2064V-80LT44I

ISPLSI2064V-80LT44I

更新时间： 2024-10-27 21:55:07

品牌	Logo	应用领域
莱迪思 - LATTICE		可编程逻辑
页数	文件大小	规格书
14页	140K
描述
3.3V High Density Programmable Logic

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ispLSI 2064V

3.3V High Density Programmable Logic

Features

Functional Block Diagram

• HIGH DENSITY PROGRAMMABLE LOGIC

Input Bus

— 2000 PLD Gates

Output Routing Pool (ORP)

— 64 and 32 I/O Pin Versions, Four Dedicated Inputs

— 64 Registers

— High Speed Global Interconnect

— Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

— Small Logic Block Size for Random Logic

Global Routing Pool

(GRP)

• 3.3V LOW VOLTAGE 2064 ARCHITECTURE

— Interfaces with Standard 5V TTL Devices

— The 64 I/O Pin Version is Fuse Map Compatible with

5V ispLSI 2064

• HIGH-PERFORMANCE E²CMOS^®TECHNOLOGY

Logic

Array

GLB

— fmax = 100MHz Maximum Operating Frequency

— tpd = 7.5ns Propagation Delay

— Electrically Erasable and Reprogrammable

— Non-Volatile

Output Routing Pool (ORP)

Input Bus

— 100% Tested at Time of Manufacture

— Unused Product Term Shutdown Saves Power

0139A/2064V

• IN-SYSTEM PROGRAMMABLE

— 3.3V In-System Programmability (ISP™) Using

Boundary Scan Test Access Port (TAP)

Description

The ispLSI 2064V is a High Density Programmable Logic

Device available in 64 and 32 I/O-pin versions. The

device contains 64 Registers, four Dedicated Input pins,

three Dedicated Clock Input pins, two dedicated Global

OE input pins and a Global Routing Pool (GRP). The

GRP provides complete interconnectivity between all of

these elements. The ispLSI 2064V features in-system

programmability through the Boundary Scan Test Ac-

cess Port (TAP). The ispLSI 2064V offers non-volatile

reprogrammability of the logic, as well as the intercon-

nect, to provide truly reconfigurable systems.

— Open-Drain Output Option for Flexible Bus Interface

Capability, Allowing Easy Implementation of Wired-OR

or Bus Arbitration Logic

— Increased Manufacturing Yields, Reduced Time-to-

Market and Improved Product Quality

— Reprogram Soldered Devices for Faster Prototyping

• THE EASE OF USE AND FAST SYSTEM SPEED OF

PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAs

— Enhanced Pin Locking Capability

— Three Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control

— Flexible Pin Placement

The basic unit of logic on the ispLSI 2064V device is the

Generic Logic Block (GLB). The GLBs are labeled A0,

A1…B7(seeFigure1). Thereareatotalof16GLBsinthe

ispLSI 2064V device. Each GLB is made up of four

macrocells. Each GLB has 18 inputs, a programmable

AND/OR/ExclusiveORarray, andfouroutputswhichcan

be configured to be either combinatorial or registered.

Inputs to the GLB come from the GRP and dedicated

inputs. All of the GLB outputs are brought back into the

GRP so that they can be connected to the inputs of any

GLB on the device.

— Optimized Global Routing Pool Provides Global

Interconnectivity

• ispDesignEXPERT™ – LOGIC COMPILER AND COM-

PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL

SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

— Superior Quality of Results

— Tightly Integrated with Leading CAE Vendor Tools

— Productivity Enhancing Timing Analyzer, Explore

Tools, Timing Simulator and ispANALYZER™

— PC and UNIX Platforms

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

September 2000

2064v_10

12 3 4 5 6 7...14

中文翻译

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与ISPLSI2064V-80LT44I相关器件

型号	品牌	获取价格	描述	数据表
ISPLSI2064VE	LATTICE	获取价格	3.3V In-System Programmable High Density Supe
ISPLSI2064VE-100LB	LATTICE	获取价格	EE PLD, 5ns, CMOS, PBGA100, BGA-100
ISPLSI2064VE-100LB100	LATTICE	获取价格	3.3V In-System Programmable High Density Supe
ISPLSI2064VE-100LJ44	LATTICE	获取价格	3.3V In-System Programmable High Density Supe
ISPLSI2064VE-100LT	LATTICE	获取价格	EE PLD, 5ns, CMOS, PQFP100, TQFP-100
ISPLSI2064VE-100LT100	LATTICE	获取价格	3.3V In-System Programmable High Density Supe
ISPLSI2064VE-100LT44	LATTICE	获取价格	3.3V In-System Programmable High Density Supe
ISPLSI2064VE-100LTN100	LATTICE	获取价格	EE PLD, 13ns, 64-Cell, CMOS, PQFP100, 14 X 14 MM, 0.50 MM PITCH, LEAD FREE, TQFP-100
ISPLSI2064VE-135LB100	LATTICE	获取价格	3.3V In-System Programmable High Density Supe
ISPLSI2064VE-135LJ44	LATTICE	获取价格	3.3V In-System Programmable High Density Supe

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