Datasheet > ISPLSI2064VE-135LB100

ISPLSI2064VE-135LB100

更新时间： 2024-10-27 22:16:11

品牌	Logo	应用领域
莱迪思 - LATTICE		/
页数	文件大小	规格书
15页	200K
描述
3.3V In-System Programmable High Density SuperFAST⑩ PLD

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ISPLSI2064VE-135LB100 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	10 X 10 MM, 0.80 MM PITCH, CABGA-100
针数：	100	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.83	其他特性：	YES
最大时钟频率：	100 MHz	系统内可编程：	YES
JESD-30 代码：	S-PBGA-B100	JESD-609代码：	e0
JTAG BST：	NO	长度：	10 mm
湿度敏感等级：	3	专用输入次数：
I/O 线路数量：	64	宏单元数：	64
端子数量：	100	最高工作温度：	70 °C
最低工作温度：		组织：	0 DEDICATED INPUTS, 64 I/O
输出函数：	MACROCELL	封装主体材料：	PLASTIC/EPOXY
封装代码：	LFBGA	封装等效代码：	QFP100,.63SQ,20
封装形状：	SQUARE	封装形式：	GRID ARRAY, LOW PROFILE, FINE PITCH
电源：	3.3 V	可编程逻辑类型：	EE PLD
传播延迟：	7.5 ns	认证状态：	Not Qualified
座面最大高度：	1.5 mm	子类别：	Programmable Logic Devices
最大供电电压：	3.6 V	最小供电电压：	3 V
标称供电电压：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn63Pb37)	端子形式：	BALL
端子节距：	0.8 mm	端子位置：	BOTTOM
宽度：	10 mm	Base Number Matches：	1

ISPLSI2064VE-135LB100 数据手册

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ispLSI 2064VE

3.3V In-System Programmable

High Density SuperFAST™ PLD

Features

Functional Block Diagram

• SuperFAST HIGH DENSITY PROGRAMMABLE LOGIC

— 2000 PLD Gates

Input Bus

— 64 and 32 I/O Pin Versions, Four Dedicated Inputs

— 64 Registers

— High Speed Global Interconnect

— Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

— Small Logic Block Size for Random Logic

— 100% Functional, JEDEC and Pinout Compatible with

ispLSI 2064V Devices

Output Routing Pool (ORP)

Global Routing Pool

(GRP)

• 3.3V LOW VOLTAGE 2064 ARCHITECTURE

— Interfaces with Standard 5V TTL Devices

Logic

Array

GLB

• HIGH-PERFORMANCE E²CMOS^®TECHNOLOGY

— fmax = 280MHz* Maximum Operating Frequency

— tpd = 3.5ns* Propagation Delay

— Electrically Erasable and Reprogrammable

— Non-Volatile

Output Routing Pool (ORP)

Input Bus

— 100% Tested at Time of Manufacture

— Unused Product Term Shutdown Saves Power

0139A/2064V

• IN-SYSTEM PROGRAMMABLE

— 3.3V In-System Programmability (ISP™) Using

Boundary Scan Test Access Port (TAP)

Description

The ispLSI 2064VE is a High Density Programmable

Logic Device available in 64 and 32 I/O-pin versions. The

device contains 64 Registers, four Dedicated Input pins,

three Dedicated Clock Input pins, two dedicated Global

OE input pins and a Global Routing Pool (GRP). The

GRP provides complete interconnectivity between all of

these elements. The ispLSI 2064VE features in-system

programmability through the Boundary Scan Test Ac-

cess Port (TAP) and is 100% IEEE 1149.1 Boundary

Scan Testable. The ispLSI 2064VE offers non-volatile

reprogrammability of the logic, as well as the intercon-

nect, to provide truly reconfigurable systems.

— Open-Drain Output Option for Flexible Bus Interface

Capability, Allowing Easy Implementation of Wired-OR

or Bus Arbitration Logic

— Increased Manufacturing Yields, Reduced Time-to-

Market and Improved Product Quality

— Reprogram Soldered Devices for Faster Prototyping

• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE

• THE EASE OF USE AND FAST SYSTEM SPEED OF

PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAs

— Enhanced Pin Locking Capability

— Three Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

Interconnectivity

The basic unit of logic on the ispLSI 2064VE device is the

Generic Logic Block (GLB). The GLBs are labeled A0,

A1…B7(seeFigure1). Thereareatotalof16GLBsinthe

ispLSI 2064VE device. Each GLB is made up of four

macrocells. Each GLB has 18 inputs, a programmable

AND/OR/ExclusiveORarray, andfouroutputswhichcan

be configured to be either combinatorial or registered.

Inputs to the GLB come from the GRP and dedicated

inputs. All of the GLB outputs are brought back into the

GRP so that they can be connected to the inputs of any

GLB on the device.

• ispDesignEXPERT™ – LOGIC COMPILER AND COM-

PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL

SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

— Superior Quality of Results

— Tightly Integrated with Leading CAE Vendor Tools

— Productivity Enhancing Timing Analyzer, Explore

Tools, Timing Simulator and ispANALYZER™

— PC and UNIX Platforms

*Advanced Information

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

September 2000

2064ve_06

12 3 4 5 6 7...15

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与ISPLSI2064VE-135LB100相关器件

型号	品牌	获取价格	描述	数据表
ISPLSI2064VE-135LJ44	LATTICE	获取价格	3.3V In-System Programmable High Density Supe
ISPLSI2064VE-135LT	LATTICE	获取价格	EE PLD, 5ns, CMOS, PQFP100, TQFP-100
ISPLSI2064VE-135LT100	LATTICE	获取价格	3.3V In-System Programmable High Density Supe
ISPLSI2064VE-135LT100I	LATTICE	获取价格	3.3V In-System Programmable High Density Supe
ISPLSI2064VE-135LT44	LATTICE	获取价格	3.3V In-System Programmable High Density Supe
ISPLSI2064VE-135LT44I	LATTICE	获取价格	3.3V In-System Programmable High Density Supe
ISPLSI2064VE-135LTN44	LATTICE	获取价格	EE PLD, 7.5ns, 64-Cell, CMOS, PQFP44, 10 X 10 MM, 0.80 MM PITCH, LEAD FREE, TQFP-44
ISPLSI2064VE-135LTN44I	LATTICE	获取价格	EE PLD, 7.5ns, 64-Cell, CMOS, PQFP44, 10 X 10 MM, 0.80 MM PITCH, LEAD FREE, TQFP-44
ISPLSI2064VE-180LB	LATTICE	获取价格	EE PLD, 5ns, CMOS, PBGA100, BGA-100
ISPLSI2064VE-180LJ84	LATTICE	获取价格	EE PLD, 7.5ns, CMOS, PQCC84, PLASTIC, LCC-84

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