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ISPLSI2064VL-135LT100 PDF预览

ISPLSI2064VL-135LT100

更新时间： 2024-10-27 22:15:47
品牌 Logo 应用领域
莱迪思 - LATTICE /
页数 文件大小 规格书
14页 188K
描述
2.5V In-System Programmable SuperFAST⑩ High Density PLD

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ISPLSI2064VL-135LT100 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QFP包装说明：TQFP-100
针数：100Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.78其他特性：YES
最大时钟频率：95 MHz系统内可编程：YES
JESD-30 代码：S-PQFP-G100JESD-609代码：e0
JTAG BST：YES长度：14 mm
湿度敏感等级：3专用输入次数：
I/O 线路数量：64宏单元数：64
端子数量：100最高工作温度：70 °C
最低工作温度：组织：0 DEDICATED INPUTS, 64 I/O
输出函数：MACROCELL封装主体材料：PLASTIC/EPOXY
封装代码：LFQFP封装等效代码：QFP100,.63SQ,20
封装形状：SQUARE封装形式：FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）：240电源：2.5 V
可编程逻辑类型：EE PLD传播延迟：10 ns
认证状态：Not Qualified座面最大高度：1.6 mm
子类别：Programmable Logic Devices最大供电电压：2.7 V
最小供电电压：2.3 V标称供电电压：2.5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：14 mmBase Number Matches：1

ISPLSI2064VL-135LT100 数据手册

 浏览型号ISPLSI2064VL-135LT100的Datasheet PDF文件第2页浏览型号ISPLSI2064VL-135LT100的Datasheet PDF文件第3页浏览型号ISPLSI2064VL-135LT100的Datasheet PDF文件第4页浏览型号ISPLSI2064VL-135LT100的Datasheet PDF文件第5页浏览型号ISPLSI2064VL-135LT100的Datasheet PDF文件第6页浏览型号ISPLSI2064VL-135LT100的Datasheet PDF文件第7页 
®
ispLSI 2064VL  
2.5V In-System Programmable  
SuperFAST™ High Density PLD  
Features  
Functional Block Diagram  
• SuperFAST HIGH DENSITY PROGRAMMABLE LOGIC  
Input Bus  
— 2000 PLD Gates  
Output Routing Pool (ORP)  
— 64 and 32 I/O Pin Versions, Four Dedicated Inputs  
— 64 Registers  
B7  
B6  
B5  
B4  
— High Speed Global Interconnect  
— Wide Input Gating for Fast Counters, State  
Machines, Address Decoders, etc.  
— Small Logic Block Size for Random Logic  
— 100% Functional, JEDEC and Pinout Compatible with  
ispLSI 2064V and 2064VE Devices  
Global Routing Pool  
(GRP)  
A0  
A1  
A2  
A3  
B3  
B2  
B1  
B0  
D
D
D
D
Q
Q
Q
Q
• 2.5V LOW VOLTAGE 2064 ARCHITECTURE  
Logic  
Array  
GLB  
— Interfaces with Standard 3.3V TTL Devices (Inputs  
and I/Os are 3.3V Tolerant)  
— 60 mA Typical Active Current  
• HIGH-PERFORMANCE E2CMOS® TECHNOLOGY  
A4  
A5  
A6  
A7  
— fmax = 165MHz Maximum Operating Frequency  
— tpd = 5.5ns Propagation Delay  
Output Routing Pool (ORP)  
Input Bus  
— Electrically Erasable and Reprogrammable  
— Non-Volatile  
0139A/2064VL  
— 100% Tested at Time of Manufacture  
— Unused Product Term Shutdown Saves Power  
Description  
• IN-SYSTEM PROGRAMMABLE  
The ispLSI 2064VL is a High Density Programmable  
Logic Device available in 64 and 32 I/O-pin versions. The  
device contains 64 Registers, four Dedicated Input pins,  
three Dedicated Clock Input pins, two dedicated Global  
OE input pins and a Global Routing Pool (GRP). The  
GRP provides complete interconnectivity between all of  
these elements. The ispLSI 2064VL features in-system  
programmability through the Boundary Scan Test Ac-  
cess Port (TAP) and is 100% IEEE 1149.1 Boundary  
Scan Testable. The ispLSI 2064VL offers non-volatile  
reprogrammability of the logic, as well as the intercon-  
nect, to provide truly reconfigurable systems.  
— 2.5V In-System Programmability (ISP™) Using  
Boundary Scan Test Access Port (TAP)  
— Open-Drain Output Option for Flexible Bus Interface  
Capability, Allowing Easy Implementation of Wired-OR  
or Bus Arbitration Logic  
— Increased Manufacturing Yields, Reduced Time-to-  
Market and Improved Product Quality  
— Reprogram Soldered Devices for Faster Prototyping  
• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE  
• THE EASE OF USE AND FAST SYSTEM SPEED OF  
PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAs  
— Enhanced Pin Locking Capability  
— Three Dedicated Clock Input Pins  
— Synchronous and Asynchronous Clocks  
— Programmable Output Slew Rate Control  
— Flexible Pin Placement  
The basic unit of logic on the ispLSI 2064VL device is the  
Generic Logic Block (GLB). The GLBs are labeled A0,  
A1…B7(seeFigure1). Thereareatotalof16GLBsinthe  
ispLSI 2064VL device. Each GLB is made up of four  
macrocells. Each GLB has 18 inputs, a programmable  
AND/OR/ExclusiveORarray, andfouroutputswhichcan  
be configured to be either combinatorial or registered.  
Inputs to the GLB come from the GRP and dedicated  
inputs. All of the GLB outputs are brought back into the  
GRP so that they can be connected to the inputs of any  
GLB on the device.  
— Optimized Global Routing Pool Provides Global  
Interconnectivity  
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-  
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL  
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING  
— Superior Quality of Results  
— Tightly Integrated with Leading CAE Vendor Tools  
— Productivity Enhancing Timing Analyzer, Explore  
Tools, Timing Simulator and ispANALYZER™  
— PC and UNIX Platforms  
Copyright©2000LatticeSemiconductorCorp.Allbrandorproductnamesaretrademarksorregisteredtrademarksoftheirrespectiveholders. Thespecificationsandinformationhereinaresubject  
to change without notice.  
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.  
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com  
September 2000  
2064vl_02  
1
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ISPLSI2064VL-135LT100 替代型号

型号 品牌 替代类型 描述 数据表
ISPLSI2064VL-165LT100 LATTICE

功能相似

 2.5V In-System Programmable SuperFAST⑩ High D
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