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ISPLSI2032VE-110LT48 PDF预览

ISPLSI2032VE-110LT48

更新时间： 2024-09-15 22:12:55
品牌 Logo 应用领域
莱迪思 - LATTICE /
页数 文件大小 规格书
14页 180K
描述
3.3V In-System Programmable High Density SuperFAST⑩ PLD

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ISPLSI2032VE-110LT48 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：QFP
包装说明：7 X 7 MM, 0.50 MM PITCH, TQFP-48针数：48
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.69
其他特性：YES最大时钟频率：77 MHz
系统内可编程：YESJESD-30 代码：S-PQFP-G48
JESD-609代码：e0JTAG BST：NO
长度：7 mm湿度敏感等级：3
专用输入次数：I/O 线路数量：32
宏单元数：32端子数量：48
最高工作温度：70 °C最低工作温度：
组织：0 DEDICATED INPUTS, 32 I/O输出函数：MACROCELL
封装主体材料：PLASTIC/EPOXY封装代码：TFQFP
封装等效代码：QFP48,.35SQ,20封装形状：SQUARE
封装形式：FLATPACK, THIN PROFILE, FINE PITCH峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3.3 V可编程逻辑类型：EE PLD
传播延迟：13 ns认证状态：Not Qualified
座面最大高度：1.2 mm子类别：Programmable Logic Devices
最大供电电压：3.6 V最小供电电压：3 V
标称供电电压：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：TIN LEAD端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：7 mm
Base Number Matches：1

ISPLSI2032VE-110LT48 数据手册

 浏览型号ISPLSI2032VE-110LT48的Datasheet PDF文件第2页浏览型号ISPLSI2032VE-110LT48的Datasheet PDF文件第3页浏览型号ISPLSI2032VE-110LT48的Datasheet PDF文件第4页浏览型号ISPLSI2032VE-110LT48的Datasheet PDF文件第5页浏览型号ISPLSI2032VE-110LT48的Datasheet PDF文件第6页浏览型号ISPLSI2032VE-110LT48的Datasheet PDF文件第7页 
®
ispLSI 2032VE  
3.3V In-System Programmable  
High Density SuperFAST™ PLD  
Features  
Functional Block Diagram  
• SuperFAST HIGH DENSITY IN-SYSTEM  
PROGRAMMABLE LOGIC  
— 1000 PLD Gates  
— 32 I/O Pins, Two Dedicated Inputs  
— 32 Registers  
— High Speed Global Interconnect  
— Wide Input Gating for Fast Counters, State  
Machines, Address Decoders, etc.  
— Small Logic Block Size for Random Logic  
— 100% Functional, JEDEC and Pinout Compatible  
with ispLSI 2032V Devices  
Global Routing Pool  
(GRP)  
A0  
A1  
A2  
A7  
A6  
A5  
A4  
D
D
D
D
Q
Q
Q
Q
• 3.3V LOW VOLTAGE 2032 ARCHITECTURE  
— Interfaces With Standard 5V TTL Devices  
Logic  
Array  
GLB  
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY  
— fmax = 225 MHz Maximum Operating Frequency  
— tpd = 4.0 ns Propagation Delay  
A3  
— Electrically Erasable and Reprogrammable  
— Non-Volatile  
— 100% Tested at Time of Manufacture  
— Unused Product Term Shutdown Saves Power  
0139Bisp/2000  
Description  
• IN-SYSTEM PROGRAMMABLE  
— 3.3V In-System Programmability Using Boundary  
Scan Test Access Port (TAP)  
The ispLSI 2032VE is a High Density Programmable  
Logic Device that can be used in both 3.3V and 5V  
systems. Thedevicecontains32Registers, 32Universal  
I/O pins, two Dedicated Input Pins, three Dedicated  
Clock Input Pins, one dedicated Global OE input pin and  
a Global Routing Pool (GRP). The GRP provides  
completeinterconnectivitybetweenalloftheseelements.  
The ispLSI 2032VE features in-system programmability  
through the Boundary Scan Test Access Port (TAP) and  
is 100% IEEE 1149.1 Boundary Scan Testable. The  
ispLSI 2032VE offers non-volatile reprogrammability of  
the logic, as well as the interconnect to provide truly  
reconfigurable systems.  
— Open-Drain Output Option for Flexible Bus Interface  
Capability, Allowing Easy Implementation of  
Wired-OR or Bus Arbitration Logic  
— Increased Manufacturing Yields, Reduced Time-to-  
Market and Improved Product Quality  
— Reprogram Soldered Devices for Faster Prototyping  
• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE  
• THE EASE OF USE AND FAST SYSTEM SPEED OF  
PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAs  
— Enhanced Pin Locking Capability  
— Three Dedicated Clock Input Pins  
— Synchronous and Asynchronous Clocks  
— Programmable Output Slew Rate Control  
— Flexible Pin Placement  
The basic unit of logic on the ispLSI 2032VE device is the  
Generic Logic Block (GLB). The GLBs are labeled A0, A1  
.. A7 (see Figure 1). There are a total of eight GLBs in the  
ispLSI 2032VE device. Each GLB is made up of four  
macrocells. Each GLB has 18 inputs, a programmable  
AND/OR/ExclusiveORarray, andfouroutputswhichcan  
be configured to be either combinatorial or registered.  
Inputs to the GLB come from the GRP and dedicated  
inputs. All of the GLB outputs are brought back into the  
GRP so that they can be connected to the inputs of any  
GLB on the device.  
— Optimized Global Routing Pool Provides Global  
Interconnectivity  
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-  
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL  
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING  
— Superior Quality of Results  
— Tightly Integrated with Leading CAE Vendor Tools  
— Productivity Enhancing Timing Analyzer, Explore  
Tools, Timing Simulator and ispANALYZER™  
— PC and UNIX Platforms  
Copyright©2000LatticeSemiconductorCorp. Allbrandorproductnamesaretrademarksorregisteredtrademarksoftheirrespectiveholders. Thespecificationsandinformationhereinaresubject  
to change without notice.  
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.  
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com  
September 2000  
2032ve_07  
1
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ISPLSI2032VE-110LT48 替代型号

型号 品牌 替代类型 描述 数据表
ISPLSI2032VE-135LT48 LATTICE

完全替代

 3.3V In-System Programmable High Density Supe
M4A3-32/32-10VNC48 LATTICE

类似代替

 EE PLD, 10ns, 32-Cell, CMOS, PQFP48, 1.40 MM HEIGHT, LEAD FREE, TQFP-48
M4A3-32/32-7VNC48 LATTICE

类似代替

 EE PLD, 7.5ns, 32-Cell, CMOS, PQFP48, 1.40 MM HEIGHT, LEAD FREE, TQFP-48

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ISPLSI2032VE135LB49 LATTICE

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