5秒后页面跳转
捷配首页

Datasheet > ISPLSI2032A-135LTN48
ISPLSI2032A-135LTN48 PDF预览

ISPLSI2032A-135LTN48

更新时间： 2024-11-05 14:34:07
品牌 Logo 应用领域
莱迪思 - LATTICE 时钟输入元件可编程逻辑
页数 文件大小 规格书
16页 406K
描述
EE PLD, 10ns, 32-Cell, CMOS, PQFP48, LEAD FREE, TQFP-48

阅读下载

中文翻译

获取价格

ISPLSI2032A-135LTN48 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：QFP
包装说明：FQFP, QFP44,.47SQ,32针数：48
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.72
其他特性：YES最大时钟频率：100 MHz
系统内可编程：YESJESD-30 代码：S-PQFP-G48
JESD-609代码：e3JTAG BST：NO
长度：7 mm湿度敏感等级：3
专用输入次数：I/O 线路数量：32
宏单元数：32端子数量：48
最高工作温度：70 °C最低工作温度：
组织：0 DEDICATED INPUTS, 32 I/O输出函数：MACROCELL
封装主体材料：PLASTIC/EPOXY封装代码：FQFP
封装等效代码：QFP44,.47SQ,32封装形状：SQUARE
封装形式：FLATPACK, FINE PITCH峰值回流温度（摄氏度）：240
电源：5 V可编程逻辑类型：EE PLD
传播延迟：10 ns认证状态：Not Qualified
子类别：Programmable Logic Devices最大供电电压：5.25 V
最小供电电压：4.75 V标称供电电压：5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7 mmBase Number Matches：1

ISPLSI2032A-135LTN48 数据手册

 浏览型号ISPLSI2032A-135LTN48的Datasheet PDF文件第2页浏览型号ISPLSI2032A-135LTN48的Datasheet PDF文件第3页浏览型号ISPLSI2032A-135LTN48的Datasheet PDF文件第4页浏览型号ISPLSI2032A-135LTN48的Datasheet PDF文件第5页浏览型号ISPLSI2032A-135LTN48的Datasheet PDF文件第6页浏览型号ISPLSI2032A-135LTN48的Datasheet PDF文件第7页 
Lead-  
ee  
Fr  
®
Package  
ispLSI 2032/A  
Options  
vailable!  
A
In-System Programmable High Density PLD  
Features  
Functional Block Diagram  
• ENHANCEMENTS  
— ispLSI 2032A is Fully Form and Function Compatible  
to the ispLSI 2032, with Identical Timing  
Specifcations and Packaging  
— ispLSI 2032A is Built on an Advanced 0.35 Micron  
E2CMOS® Technology  
• HIGH DENSITY PROGRAMMABLE LOGIC  
Global Routing Pool  
A0  
A1  
A2  
A7  
A6  
A5  
A4  
(GRP)  
— 1000 PLD Gates  
— 32 I/O Pins, Two Dedicated Inputs  
— 32 Registers  
— High Speed Global Interconnect  
— Wide Input Gating for Fast Counters, State  
Machines, Address Decoders, etc.  
— Small Logic Block Size for Random Logic  
D
D
D
D
Q
Q
Q
Q
Logic  
Array  
GLB  
A3  
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY  
— fmax = 180 MHz Maximum Operating Frequency  
— tpd = 5.0 ns Propagation Delay  
— TTL Compatible Inputs and Outputs  
— Electrically Erasable and Reprogrammable  
— Non-Volatile  
0139Bisp/2000  
— 100% Tested at Time of Manufacture  
— Unused Product Term Shutdown Saves Power  
Description  
• IN-SYSTEM PROGRAMMABLE  
The ispLSI 2032 and 2032A are High Density Program-  
mable Logic Devices. The devices contain 32 Registers,  
32 Universal I/O pins, two Dedicated Input Pins, three  
Dedicated Clock Input Pins, one dedicated Global OE  
input pin and a Global Routing Pool (GRP). The GRP  
provides complete interconnectivity between all of these  
elements. The ispLSI 2032 and 2032A feature 5V in-  
system programmability and in-system diagnostic  
capabilities. The ispLSI 2032 and 2032A offer non-  
volatile reprogrammability of the logic, as well as the  
interconnect to provide truly reconfigurable systems.  
— In-System Programmable (ISP™) 5V Only  
— Increased Manufacturing Yields, Reduced Time-to-  
Market and Improved Product Quality  
— Reprogram Soldered Devices for Faster Prototyping  
• OFFERS THE EASE OF USE AND FAST SYSTEM  
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY  
OF FIELD PROGRAMMABLE GATE ARRAYS  
— Complete Programmable Device Can Combine Glue  
Logic and Structured Designs  
— Enhanced Pin Locking Capability  
— Three Dedicated Clock Input Pins  
— Synchronous and Asynchronous Clocks  
— Programmable Output Slew Rate Control to  
Minimize Switching Noise  
— Flexible Pin Placement  
— Optimized Global Routing Pool Provides Global  
Interconnectivity  
The basic unit of logic on these devices is the Generic  
Logic Block (GLB). The GLBs are labeled A0, A1 .. A7  
(Figure 1). There are a total of eight GLBs in the ispLSI  
2032 and 2032A devices. Each GLB is made up of four  
macrocells. Each GLB has 18 inputs, a programmable  
AND/OR/ExclusiveORarray, andfouroutputswhichcan  
be configured to be either combinatorial or registered.  
Inputs to the GLB come from the GRP and dedicated  
inputs. All of the GLB outputs are brought back into the  
GRP so that they can be connected to the inputs of any  
GLB on the device.  
— Lead-Free Package Options  
Copyright©2006LatticeSemiconductorCorp. Allbrandorproductnamesaretrademarksorregisteredtrademarksoftheirrespectiveholders. Thespecificationsandinformationhereinaresubject  
to change without notice.  
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.  
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com  
August 2006  
2032_11  
1
1234567...16

中文翻译

下载PDF

与ISPLSI2032A-135LTN48相关器件

型号 品牌 获取价格 描述 数据表
ISPLSI2032A-150LJ LATTICE

获取价格

 		In-System Programmable High Density PLD
ISPLSI2032A-150LJ44 LATTICE

获取价格

 		EE PLD, 8ns, 32-Cell, CMOS, PQCC44, PLASTIC, LCC-44
ISPLSI2032A-150LJI LATTICE

获取价格

 		In-System Programmable High Density PLD
ISPLSI2032A-150LT44 LATTICE

获取价格

 		In-System Programmable High Density PLD
ISPLSI2032A-150LT44I LATTICE

获取价格

 		In-System Programmable High Density PLD
ISPLSI2032A-150LT48 LATTICE

获取价格

 		In-System Programmable High Density PLD
ISPLSI2032A-150LT48I LATTICE

获取价格

 		In-System Programmable High Density PLD
ISPLSI2032A-180LJ LATTICE

获取价格

 		In-System Programmable High Density PLD
ISPLSI2032A-180LJI LATTICE

获取价格

 		In-System Programmable High Density PLD
ISPLSI2032A-180LJN44 LATTICE

获取价格

 		EE PLD, 7.5ns, 32-Cell, CMOS, PQCC44, LEAD FREE, PLASTIC, LCC-44

与ISPLSI2032A-135LTN48相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证