Datasheet > ISPLSI1048-70LQ

ISPLSI1048-70LQ

更新时间： 2024-11-13 23:59:51

品牌	Logo	应用领域
其他 - ETC		可编程逻辑器件输入元件时钟
页数	文件大小	规格书
12页	123K
描述
Electrically-Erasable Complex PLD

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ISPLSI1048-70LQ 数据手册

ispLSI 1048

In-System Programmable High Density PLD

Features

Functional Block Diagram

• HIGH-DENSITY PROGRAMMABLE LOGIC

— 8000 PLD Gates

Output Routing Pool

F7 F6 F5 F4 F3 F2 F1 F0

E7 E6 E5 E4 E3 E2 E1 E0

— 96 I/O Pins, Ten Dedicated Inputs

— 288 Registers

— High-Speed Global Interconnects

— Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

— Small Logic Block Size for Random Logic

— Security Cell Prevents Unauthorized Copying

Logic

Array

Global Routing Pool (GRP)

GLB

• HIGH PERFORMANCE E²CMOS^®TECHNOLOGY

— fmax = 80 MHz Maximum Operating Frequency

B0 B1 B2 B3 B4 B5 B6 B7

Output Routing Pool

C0 C1 C2 C3 C4 C5 C6 C7

Output Routing Pool

CLK

—^—t^fp^md^ax= ⁼15⁵⁰ns^MP^Hr^zo^fp^oa^rg^Iaⁿt^dio^un^stD^rie^al^la^Dy^evices

— TTL Compatible Inputs and Outputs

— Electrically Erasable and Reprogrammable

— Non-Volatile E²CMOS Technology

— 100% Tested

Description

The ispLSI 1048 is a High-Density Programmable Logic

Device which contain 288 Registers, 96 Universal I/O

pins, ten Dedicated Input pins, four Dedicated Clock

Input pins and a Global Routing Pool (GRP). The GRP

provides complete interconnectivity between all of these

elements. The ispLSI 1048 features 5-Volt in-system

programming and in-system diagnostic capabilities. It is

thefirstdevicewhichoffersnon-volatilereprogrammability

of the logic, as well as the interconnect to provide truly

reconfigurable systems.

• IN-SYSTEM PROGRAMMABLE

— In-System Programmable™ (ISP™) 5-Volt Only

— Increased Manufacturing Yields, Reduced Time-to-

Market, and Improved Product Quality

— Reprogram Soldered Devices for Faster Debugging

• COMBINES EASE OF USE AND THE FAST SYSTEM

SPEED OF PLDs WITH THE DENSITY AND FLEX-

IBILITY OF FIELD PROGRAMMABLE GATE ARRAYS

— Complete Programmable Device Can Combine Glue

Logic and Structured Designs

— Four Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

Interconnectivity

The basic unit of logic on the ispLSI 1048 devices is the

Generic Logic Block (GLB). The GLBs are labeled A0, A1

.. F7 (see figure 1). There are a total of 48 GLBs in the

ispLSI 1048 device. Each GLB has 18 inputs, a program-

mable AND/OR/XOR array, and four outputs which can

be configured to be either combinatorial or registered.

Inputs to the GLB come from the GRP and dedicated

inputs. All of the GLB outputs are brought back into the

GRP so that they can be connected to the inputs of any

other GLB on the device.

• ispDesignEXPERT™ – LOGIC COMPILER AND COM-

PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL

SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

— Superior Quality of Results

— Tightly Integrated with Leading CAE Vendor Tools

— Productivity Enhancing Timing Analyzer, Explore

Tools, Timing Simulator and ispANALYZER™

— PC and UNIX Platforms

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

August 2000

1048_06

12 3 4 5 6 7...12

中文翻译

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与ISPLSI1048-70LQ相关器件

型号	品牌	获取价格	描述	数据表
ISPLSI1048-80LQ	ETC	获取价格	Electrically-Erasable Complex PLD
ISPLSI1048C	LATTICE	获取价格	In-System Programmable High Density PLD
ISPLSI1048C-50LG/883	LATTICE	获取价格	In-System Programmable High Density PLD
ISPLSI1048C-50LQ	ETC	获取价格	Electrically-Erasable Complex PLD
ISPLSI1048C-50LQI	ETC	获取价格	Electrically-Erasable Complex PLD
ISPLSI1048C-70LQ	ETC	获取价格	Electrically-Erasable Complex PLD
ISPLSI1048E	LATTICE	获取价格	In-System Programmable High Density PLD
ISPLSI1048E_06	LATTICE	获取价格	In-System Programmable High Density PLD
ISPLSI1048E100LQ	LATTICE	获取价格	In-System Programmable High Density PLD
ISPLSI1048E-100LQ	ETC	获取价格	Electrically-Erasable Complex PLD

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