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ISPLSI1048C-50LQI PDF预览

ISPLSI1048C-50LQI

更新时间: 2024-11-13 23:59:51
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页数 文件大小 规格书
14页 147K
描述
Electrically-Erasable Complex PLD

ISPLSI1048C-50LQI 数据手册

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®
ispLSI 1048C  
In-System Programmable High Density PLD  
Features  
Functional Block Diagram  
• HIGH-DENSITY PROGRAMMABLE LOGIC  
— 8000 PLD Gates  
— 96 I/O Pins, 12 Dedicated Inputs, 2 Global Output  
Enables  
— 288 Registers  
— High-Speed Global Interconnect  
— Wide Input Gating for Fast Counters, State  
Machines, Address Decoders, etc.  
— Small Logic Block Size for Random Logic  
— Security Cell Prevents Unauthorized Copying  
Output Routing Pool  
Output Routing Pool  
F7 F6 F5 F4 F3 F2 F1 F0  
E7 E6 E5 E4 E3 E2 E1 E0  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
D
D
D
D
Q
Q
Q
Q
Logic  
Array  
Global Routing Pool (GRP)  
GLB  
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY  
B0 B1 B2 B3 B4 B5 B6 B7  
Output Routing Pool  
C0 C1 C2 C3 C4 C5 C6 C7  
Output Routing Pool  
CLK  
fmax = 70 MHz Maximum Operating Frequency  
tfpmdax= =1650nsMPHrzofpoargIantdiounstDrieallaaynd Military/883 Devices  
0139G1A-isp  
— TTL Compatible Inputs and Outputs  
— Electrically Erasable and Reprogrammable  
— Non-Volatile E2CMOSTechnology  
— 100% Tested at Time of Manufacture  
Description  
TheispLSI1048CisaHigh-DensityProgrammableLogic  
Device containing 288 Registers, 96 Universal I/O pins,  
12 Dedicated Input pins, two Global Output Enables  
(GOE), four Dedicated Clock Input pins and a Global  
Routing Pool (GRP). The GRP provides complete  
interconnectivity between all of these elements. The  
ispLSI 1048C features 5-Volt in-system programming  
and in-system diagnostic capabilities. It is the first device  
which offers non-volatile reprogrammability of the logic,  
and the interconnect to provide truly reconfigurable sys-  
tems. Compared to the ispLSI 1048, the ispLSI 1048C  
offers two additional dedicated inputs and two new Glo-  
bal Output Enable pins.  
• IN-SYSTEM PROGRAMMABLE  
— In-System Programmable™ (ISP™) 5-Volt Only  
— Increased Manufacturing Yields, Reduced Time-to-  
Market, and Improved Product Quality  
— Reprogram Soldered Devices for Faster Debugging  
• COMBINES EASE OF USE AND THE FAST SYSTEM  
SPEED OF PLDs WITH THE DENSITY AND FLEX-  
IBILITY OF FIELD PROGRAMMABLE GATE ARRAYS  
— Complete Programmable Device Can Combine Glue  
Logic and Structured Designs  
— Four Dedicated Clock Input Pins  
— Synchronous and Asynchronous Clocks  
— Flexible Pin Placement  
— Optimized Global Routing Pool Provides Global  
Interconnectivity  
The basic unit of logic on the ispLSI 1048C device is the  
Generic Logic Block (GLB). The GLBs are labeled A0, A1  
.. F7 in figure 1. There are a total of 48 GLBs in the ispLSI  
1048C devices. Each GLB has 18 inputs, a program-  
mable AND/OR/XOR array, and four outputs which can  
be configured to be either combinatorial or registered.  
Inputs to the GLB come from the GRP and dedicated  
inputs. All of the GLB outputs are brought back into the  
GRP so that they can be connected to the inputs of any  
other GLB on the device.  
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-  
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL  
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING  
— Superior Quality of Results  
— Tightly Integrated with Leading CAE Vendor Tools  
— Productivity Enhancing Timing Analyzer, Explore  
Tools, Timing Simulator and ispANALYZER™  
— PC and UNIX Platforms  
Copyright©1999LatticeSemiconductorCorp. Allbrandorproductnamesaretrademarksorregisteredtrademarksoftheirrespectiveholders. Thespecificationsandinformationhereinaresubject  
to change without notice.  
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.  
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com  
August 2000  
1048C_08  
1

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