Datasheet > ISPLSI1048E-100LT

ISPLSI1048E-100LT

更新时间： 2024-11-13 23:59:51

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ISPLSI1048E-100LT 数据手册

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ispLSI 1048E

In-System Programmable High Density PLD

Features

Functional Block Diagram

• HIGH DENSITY PROGRAMMABLE LOGIC

— 8,000 PLD Gates

Output Routing Pool

F7 F6 F5 F4 F3 F2 F1 F0

E7 E6 E5 E4 E3 E2 E1 E0

— 96 I/O Pins, Twelve Dedicated Inputs

— 288 Registers

— High-Speed Global Interconnects

— Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

— Small Logic Block Size for Random Logic

— Functionally and Pin-out Compatible to ispLSI 1048C

Logic

Array

Global Routing Pool (GRP)

GLB

• HIGH PERFORMANCE E²CMOS^®TECHNOLOGY

B0 B1 B2 B3 B4 B5 B6 B7

Output Routing Pool

C0 C1 C2 C3 C4 C5 C6 C7

Output Routing Pool

— fmax = 125 MHz Maximum Operating Frequency

— tpd = 7.5 ns Propagation Delay

CLK

— TTL Compatible Inputs and Outputs

— Electrically Eraseable and Reprogrammable

— Non-Volatile

0139G1A-isp

Description

— 100% Tested at Time of Manufacture

• IN-SYSTEM PROGRAMMABLE

The ispLSI 1048E is a High Density Programmable Logic

Device containing 288 Registers, 96 Universal I/O pins,

12 Dedicated Input pins, four Dedicated Clock Input pins,

twodedicatedGlobalOEinputpins,andaGlobalRouting

Pool(GRP).TheGRPprovidescompleteinterconnectivity

between all of these elements. The ispLSI 1048E offers

5Vnon-volatilein-systemprogrammabilityofthelogic,as

well as the interconnect to provide truly reconfigurable

systems. A functional superset of the ispLSI 1048 archi-

tecture, the ispLSI 1048E device adds two new global

output enable pins and two additional dedicated inputs.

— In-System Programmable (ISP™) 5V Only

— Increased Manufacturing Yields, Reduced Time-to-

Market and Improved Product Quality

— Reprogram Soldered Devices for Faster Prototyping

• OFFERS THE EASE OF USE AND FAST SYSTEM

SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY

OF FIELD PROGRAMMABLE GATE ARRAYS

— Complete Programmable Device Can Combine Glue

Logic and Structured Designs

— Enhanced Pin Locking Capability

— Four Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control to

Minimize Switching Noise

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

Interconnectivity

The basic unit of logic on the ispLSI 1048E device is the

Generic Logic Block (GLB). The GLBs are labeled A0,

A1…F7(seeFigure1). Thereareatotalof48GLBsinthe

ispLSI 1048E device. Each GLB has 18 inputs, a pro-

grammableAND/OR/ExclusiveORarray,andfouroutputs

which can be configured to be either combinatorial or

registered. Inputs to the GLB come from the GRP and

dedicated inputs. All of the GLB outputs are brought back

into the GRP so that they can be connected to the inputs

of any other GLB on the device.

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

January 2002

1048e_11

12 3 4 5 6 7...16

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与ISPLSI1048E-100LT相关器件

型号	品牌	获取价格	描述	数据表
ISPLSI1048E100LTI	LATTICE	获取价格	In-System Programmable High Density PLD
ISPLSI1048E-100LTI	LATTICE	获取价格	EE PLD, 12.5ns, 192-Cell, CMOS, PQFP128
ISPLSI1048E100LTN	LATTICE	获取价格	In-System Programmable High Density PLD
ISPLSI1048E-100LTN	LATTICE	获取价格	EE PLD, 12.5ns, 192-Cell, CMOS, PQFP128, LEAD FREE, TQFP-128
ISPLSI1048E100LTNI	LATTICE	获取价格	In-System Programmable High Density PLD
ISPLSI1048E125LQ	LATTICE	获取价格	In-System Programmable High Density PLD
ISPLSI1048E-125LQ	ETC	获取价格	Electrically-Erasable Complex PLD
ISPLSI1048E125LQI	LATTICE	获取价格	In-System Programmable High Density PLD
ISPLSI1048E125LQN	LATTICE	获取价格	In-System Programmable High Density PLD
ISPLSI1048E125LQNI	LATTICE	获取价格	In-System Programmable High Density PLD

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