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ISP1705HN,518 PDF预览

ISP1705HN,518

更新时间: 2024-11-24 06:40:03
品牌 Logo 应用领域
恩智浦 - NXP /
页数 文件大小 规格书
89页 437K
描述
USB Bus Controller, CMOS, PQCC36, 5 X 5 MM, 0.85 MM HEIGHT, ROHS COMPLIANT, PLASTIC, MO-220, SOT818-1, HVQFN-36

ISP1705HN,518 数据手册

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ISP1705  
ULPI Hi-Speed USB transceiver  
Rev. 01 — 13 June 2008  
Product data sheet  
1. General description  
The ISP1705 is a UTMI+ Low Pin Interface (ULPI) Hi-Speed Universal Serial Bus (USB)  
transceiver that is fully compliant with Universal Serial Bus Specification Rev. 2.0,  
On-The-Go Supplement to the USB 2.0 Specification Rev. 1.3 and UTMI+ Low Pin  
Interface (ULPI) Specification Rev. 1.1.  
The ISP1705 can transmit and receive USB data at high speed (480 Mbit/s), full speed  
(12 Mbit/s) and low speed (1.5 Mbit/s), and provides a pin-optimized, physical layer  
front-end attachment to the USB host, peripheral or OTG controller with Single Data Rate  
(SDR) or Dual Data Rate (DDR) ULPI link. The ISP1705 can transparently transmit and  
receive UART signaling.  
It is ideal for use in portable electronic devices, such as mobile phones, digital still  
cameras, digital video cameras, Personal Digital Assistants (PDAs) and digital audio  
players. It allows USB Application-Specific Integrated Circuits (ASICs), Programmable  
Logic Devices (PLDs) or any system chip set to interface with the physical layer of the  
USB through an 8-pin (DDR) or 12-pin (SDR) interface.  
The ISP1705 can interface to devices with digital I/O voltages in the range of 3.0 V to  
3.6 V.  
The ISP1705 is available in HVQFN36 and TFBGA36 packages.  
2. Features  
I Fully complies with:  
N USB: Universal Serial Bus Specification Rev. 2.0  
N OTG: On-The-Go Supplement to the USB 2.0 Specification Rev. 1.3  
N ULPI: UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1  
I Interfaces to USB host, peripheral or OTG cores; optimized for portable devices or  
system ASICs with built-in ULPI link  
I Complete Hi-Speed USB physical front-end solution that supports high speed  
(480 Mbit/s), full speed (12 Mbit/s) and low speed (1.5 Mbit/s)  
N Integrated 45 Ω ± 10 % high-speed termination resistors, 1.5 kΩ ± 5 % full-speed  
device pull-up resistor, and 15 kΩ ± 5 % host termination resistors  
N Integrated parallel-to-serial and serial-to-parallel converters to transmit and receive  
N USB clock and data recovery to receive USB data up to ±500 ppm  
N Insertion of stuff bits during transmit and discarding of stuff bits during receive  
N Non-Return-to-Zero Inverted (NRZI) encoding and decoding  
N Supports bus reset, suspend, resume and high-speed detection handshake (chirp)  

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