ISP1761ET-S

更新时间： 2024-10-28 13:01:35

品牌	Logo	应用领域
恩智浦 - NXP		控制器
页数	文件大小	规格书
158页	689K
描述
暂无描述

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

ISP1761ET-S 数据手册

ISP1761

Hi-Speed Universal Serial Bus On-The-Go controller

Rev. 01 — 12 January 2005

Product data sheet

1. General description

The ISP1761 is a single-chip Hi-Speed Universal Serial Bus (USB) On-The-Go (OTG)

Controller integrated with the advanced Philips Slave Host Controller and the Philips

ISP1582 Peripheral Controller.

The Hi-Speed USB Host Controller and Peripheral Controller comply to Universal Serial

Bus Speciﬁcation Rev. 2.0 and support data transfer speeds of up to 480 Mbit/s. The

Enhanced Host Controller Interface (EHCI) core implemented in the Host Controller is

adapted from Enhanced Host Controller Interface Speciﬁcation for Universal Serial Bus

Rev. 1.0. The OTG controller is compliant with On-The-Go Supplement to the USB

Speciﬁcation Rev. 1.0a.

The ISP1761 has three USB ports. Port 1 can be conﬁgured to function as a downstream

port, an upstream port or an OTG port; ports 2 and 3 are always conﬁgured as

downstream ports. The OTG port can switch its role from host to peripheral, and

peripheral to host. The OTG port can become a host through the Host Negotiation

Protocol (HNP) as speciﬁed in the OTG supplement.

2. Features

■ Compliant with Universal Serial Bus Speciﬁcation Rev. 2.0; supporting data transfer at

high-speed (480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s)

■ Integrated Transaction Translator (TT) for Original USB (full-speed and low-speed)

peripheral support

■ Three USB ports that support three operational modes:

◆ Mode 1: Port 1 is an OTG Controller port, and ports 2 and 3 are Host Controller

ports

◆ Mode 2: Ports 1, 2 and 3 are Host Controller ports

◆ Mode 3: Port 1 is a Peripheral Controller port, and ports 2 and 3 are Host Controller

ports

■ Supports OTG Host Negotiation Protocol (HNP) and Session Request Protocol (SRP)

■ Multitasking support with Virtual Segmentation feature (up to four banks)

■ High-speed memory controller (variable latency and SRAM external interface)

■ Directly addressable memory architecture

■ Generic processor interface to most CPUs, such as: Hitachi^®SH-3 and SH-4, Philips

XA, Intel^®StrongARM^®, NEC^®and Toshiba^®MIPS, Motorola^®DragonBall™ and

PowerPC^®Reduced Instruction Set Computer (RISC) processors

■ Conﬁgurable 32-bit and 16-bit external memory data bus

■ Supports Programmed I/O (PIO) and Direct Memory Access (DMA)

■ Slave DMA implementation on CPU interface for reducing the host system’s CPU load

12 3 4 5 6 7...158

中文翻译

下载PDF

与ISP1761ET-S相关器件

型号	品牌	获取价格	描述	数据表
ISP1763AETTM	ETC	获取价格	Hi-Speed USB OTG controller Rev. 02 â 24 Fe
ISP184	HAMMOND	获取价格	Panneaux lateraux
ISP185	HAMMOND	获取价格	Panneaux lateraux
ISP186	HAMMOND	获取价格	Panneaux lateraux
ISP188	HAMMOND	获取价格	Panneaux lateraux
ISP2032	LATTICE	获取价格	In-System Programmable Super FAST High Density PLD
ISP2032E	LATTICE	获取价格	In-System Programmable Super FAST High Density PLD
ISP204	HAMMOND	获取价格	Panneaux lateraux
ISP205	HAMMOND	获取价格	Panneaux lateraux
ISP206	HAMMOND	获取价格	Panneaux lateraux