Datasheet > ISP2100A/66

ISP2100A/66

更新时间： 2024-10-27 23:59:51

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其他 - ETC		控制器
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4页	30K
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Controller Miscellaneous - Datasheet Reference

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ISP2100A/66 数据手册

QLogic Corporation

ISP2100A Intelligent Fibre Channel Processors

Data Sheet

■ Supports 100 Mbytes/sec sustained Fibre Channel

data transfer rate

■ Initiator or target mode

Features

■ Available in two versions:

❒ 66-MHz, 64-bit PCI host bus interface

❒ 33-MHz, 64-bit PCI host bus interface

■ Onboard RISC processor to execute operations at

the I/O control-block (IOCB) level from the host

memory

■ Onboard gigabit serial transceivers

■ Supports external transceivers with a

10-bit interface

■ Compliance with PCI Local Bus Speciﬁcation

revision 2.1

■ Compliance with ANSI SCSI standard

X3.131-1994

■ Supports PCI dual-address cycle (64-bit

addressing) and cache commands

■ No host intervention required to execute SCSI

operations from start to ﬁnish

■ Simultaneous, multiple logical threads

■ Full duplex frame buffer architecture

■ Supports JTAG boundary scan

■ Supports all Fibre Channel topologies and classes

of service

■ Compliance with Fibre Channel Arbitrated Loop

(FC-AL) Direct Disk Attach Proﬁle and Fibre

Channel Public Loop (FC-PL) Fabric Loop Attach

Proﬁle, class 2 and class 3 service

■ Compliance with PCI Bus Power Management

Interface Speciﬁcation Revision 1.0 (PC97)

ISP2100A

PCI INTERFACE

FRAME BUFFER

FIBRE ENGINE

FIBRE

CHANNEL

RECEIVE DATA

DMA CHANNEL

GIGABIT

LOOP

SERIAL

RECEIVE FRAME

BUFFER

RECEIVE

PATH

RECEIVER

LOOP

PCI

ADDRESS/DATA

64-BIT, 66-MHZ

BUS

EXT.

TRANS-

CEIVER

TRANSMIT DATA

DMA CHANNEL

LOOP

OUT

TRANSMIT FRAME

BUFFER

TRANSMIT

PATH

GIGABIT

SERIAL

TRANSMITTER

LOOP

OUT

PCI

CONTROL

COMMAND

DMA

CHANNEL

I/O BUS

CONTROL

REGISTERS

RISC

BOOT

CODE

FILE

MAILBOX

REGISTERS

CONTROL/

CONFIGURATION

REGISTERS

MEM.

I/F

ALU

ADDRESS

DATA

EXTERNAL

CODE/DATA

MEMORY

FLASH

BIOS

NVRAM

Figure 1. ISP2100A Block Diagram

83210-580-01 B

ISP2100A

12 3 4

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