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ISP1761BE-T PDF预览

ISP1761BE-T

更新时间: 2024-10-28 13:08:55
品牌 Logo 应用领域
恩智浦 - NXP 控制器
页数 文件大小 规格书
158页 689K
描述
Hi-Speed Universal Serial Bus On-The-Go controller - Application: STB, DVD recorder, DTV, media player, printer, PDA, DSC, DVC, mobile phone ; Bus interface: USB at HS (480 Mbit/s), FS (12 Mbit/s) and LS (1.5 Mbit/s) data rates ; Downstream ports: 2 ; Features: memory mapped CPU I/F to any 32-bit or16 bit I/F; 1 OTG port; Integrated patent-pending Transaction Translator supports single EHCI for HS, FS and LS transfers ; Operating/supply voltage (MAX.-Vcc,Vp,VDD): core 1.8 V; dual supply 3.0 V to 3.6 V, digital I/O I/F 1.65 V to 3.6 V V

ISP1761BE-T 技术参数

是否无铅:含铅是否Rohs认证:符合
生命周期:ActiveReach Compliance Code:unknown
风险等级:5.73Is Samacsys:N
Base Number Matches:1

ISP1761BE-T 数据手册

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ISP1761  
Hi-Speed Universal Serial Bus On-The-Go controller  
Rev. 01 — 12 January 2005  
Product data sheet  
1. General description  
The ISP1761 is a single-chip Hi-Speed Universal Serial Bus (USB) On-The-Go (OTG)  
Controller integrated with the advanced Philips Slave Host Controller and the Philips  
ISP1582 Peripheral Controller.  
The Hi-Speed USB Host Controller and Peripheral Controller comply to Universal Serial  
Bus Specification Rev. 2.0 and support data transfer speeds of up to 480 Mbit/s. The  
Enhanced Host Controller Interface (EHCI) core implemented in the Host Controller is  
adapted from Enhanced Host Controller Interface Specification for Universal Serial Bus  
Rev. 1.0. The OTG controller is compliant with On-The-Go Supplement to the USB  
Specification Rev. 1.0a.  
The ISP1761 has three USB ports. Port 1 can be configured to function as a downstream  
port, an upstream port or an OTG port; ports 2 and 3 are always configured as  
downstream ports. The OTG port can switch its role from host to peripheral, and  
peripheral to host. The OTG port can become a host through the Host Negotiation  
Protocol (HNP) as specified in the OTG supplement.  
2. Features  
Compliant with Universal Serial Bus Specification Rev. 2.0; supporting data transfer at  
high-speed (480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s)  
Integrated Transaction Translator (TT) for Original USB (full-speed and low-speed)  
peripheral support  
Three USB ports that support three operational modes:  
Mode 1: Port 1 is an OTG Controller port, and ports 2 and 3 are Host Controller  
ports  
Mode 2: Ports 1, 2 and 3 are Host Controller ports  
Mode 3: Port 1 is a Peripheral Controller port, and ports 2 and 3 are Host Controller  
ports  
Supports OTG Host Negotiation Protocol (HNP) and Session Request Protocol (SRP)  
Multitasking support with Virtual Segmentation feature (up to four banks)  
High-speed memory controller (variable latency and SRAM external interface)  
Directly addressable memory architecture  
Generic processor interface to most CPUs, such as: Hitachi® SH-3 and SH-4, Philips  
XA, Intel® StrongARM®, NEC® and Toshiba® MIPS, Motorola® DragonBall™ and  
PowerPC® Reduced Instruction Set Computer (RISC) processors  
Configurable 32-bit and 16-bit external memory data bus  
Supports Programmed I/O (PIO) and Direct Memory Access (DMA)  
Slave DMA implementation on CPU interface for reducing the host system’s CPU load  

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