ISL90840
®
Quad Digitally Controlled Potentiometers (XDCP™)
Data Sheet
July 27, 2005
FN8086.0
2
Low Noise, Low Power I C® Bus, 256 Taps
Features
The ISL90840 integrates four digitally controlled
potentiometers (XDCP) on a monolithic CMOS integrated
circuit.
• Four potentiometers in one package
• 256 resistor taps - 0.4% resolution
2
• I C serial interface
The digitally controlled potentiometers are implemented with
a combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the
- Three address pins, up to eight devices/bus
• Wiper resistance: 70Ω typical @ 3.3V
• Standby current <5µA max
2
I C bus interface. Each potentiometer has an associated
Wiper Register (WR) that can be directly written to and read
by the user. The contents of the WR controls the position of
the wiper.
• Power supply: 2.7V to 5.5V
• 50kΩ, 10kΩ total resistance
The DCPs can be used as three-terminal potentiometers or
as two-terminal variable resistors in a wide variety of
applications including control, parameter adjustments, and
signal processing.
• 20 Lead TSSOP
• Pb-free plus anneal available (RoHS compliant)
Pinout
ISL90840
(20 LEAD TSSOP)
TOP VIEW
Ordering Information
TEMP
RANGE
(°C)
RESISTANCE
OPTION
(Ω)
RH3
RL3
RW3
A2
1
20
19
18
17
16
15
14
13
12
11
RW0
RL0
RH0
D.N.C.
VCC
A1
PART NUMBER
PACKAGE
2
ISL90840UIV2027
20 Ld TSSOP -40 to +85
50K
50K
3
ISL90840UIV2027Z 20 Ld TSSOP -40 to +85
(Notes 1 & 2)
4
(Pb-Free)
SCL
SDA
GND
RW2
RL2
RH2
5
ISL90840WIV2027
20 Ld TSSOP -40 to +85
10K
10K
6
ISL90840WIV2027Z 20 Ld TSSOP -40 to +85
(Notes 1 & 2)
7
A0
(Pb-Free)
8
RH1
RL1
RW1
NOTES:
9
1. Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and
100% matte tin plate termination finish, which are RoHS
compliant and compatible with both SnPb and Pb-free soldering
operations. Intersil Pb-free products are MSL classified at Pb-
free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
10
2. Contact factory for availability.
Functional Diagram
V
R
R
R
R
H3
CC
H0
H1
H2
SCL
SDA
A0
2
I C
INTERFACE
A1
A2
GND
R
R
R
R
R
R
R
R
W3
L0
W0
L1
W1
L2
W2
L3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
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Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.