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IS62LV12816L-55BI PDF预览

IS62LV12816L-55BI

更新时间: 2024-02-28 11:43:33
品牌 Logo 应用领域
矽成 - ICSI 存储内存集成电路静态存储器
页数 文件大小 规格书
10页 463K
描述
128K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM

IS62LV12816L-55BI 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Obsolete零件包装代码:TSOP2
包装说明:TSOP2-44针数:44
Reach Compliance Code:compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.91
Is Samacsys:N最长访问时间:55 ns
其他特性:CONFIGURABLE AS 128K X 16I/O 类型:COMMON
JESD-30 代码:R-PDSO-G44JESD-609代码:e0
长度:18.41 mm内存密度:2097152 bit
内存集成电路类型:STANDARD SRAM内存宽度:16
功能数量:1端子数量:44
字数:131072 words字数代码:128000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:128KX16
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:TSOP2封装等效代码:TSOP44,.46,32
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):240
电源:3 V认证状态:Not Qualified
座面最大高度:1.2 mm最大待机电流:0.000025 A
最小待机电流:1.5 V子类别:SRAMs
最大压摆率:0.06 mA最大供电电压 (Vsup):3 V
最小供电电压 (Vsup):2.5 V标称供电电压 (Vsup):3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.8 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:10.16 mmBase Number Matches:1

IS62LV12816L-55BI 数据手册

 浏览型号IS62LV12816L-55BI的Datasheet PDF文件第4页浏览型号IS62LV12816L-55BI的Datasheet PDF文件第5页浏览型号IS62LV12816L-55BI的Datasheet PDF文件第6页浏览型号IS62LV12816L-55BI的Datasheet PDF文件第8页浏览型号IS62LV12816L-55BI的Datasheet PDF文件第9页浏览型号IS62LV12816L-55BI的Datasheet PDF文件第10页 
IS62LV12816L  
IS62LV12816LL  
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)  
-55  
-70  
-100  
Min.  
Symbol Parameter  
Min.  
55  
50  
50  
0
Max.  
—
Min.  
70  
65  
65  
0
Max.  
—
Max  
—
—
—
—
—
—
—
—
—
40  
—
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tWC  
tSCE  
tAW  
Write Cycle Time  
100  
80  
80  
0
CE to Write End  
—
—
Address Setup Time to Write End  
Address Hold from Write End  
Address Setup Time  
—
—
tHA  
—
—
tSA  
0
—
0
—
0
tPWB  
tPWE  
tSD  
LB, UB Valid to End of Write  
WE Pulse Width  
45  
45  
25  
0
—
60  
60  
30  
0
—
80  
80  
40  
0
—
—
Data Setup to Write End  
Data Hold from Write End  
WE LOW to High-Z Output  
WE HIGH to Low-Z Output  
—
—
tHD  
—
—
(3)  
tHZWE  
—
5
30  
—
—
5
30  
—
—
5
(3)  
tLZWE  
Notes:  
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.3V, input pulse levels of 0.4V to 2.2V  
and output loading specified in Figure 1.  
2. The internal write time is defined by the overlap of CE LOW, and UB or LB, and WE LOW. All signals must be in valid states to  
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the  
rising or falling edge of the signal that terminates the Write.  
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.  
AC WAVEFORMS  
WRITE CYCLE NO. 1(1,2) (CS, Controlled, OE = HIGH or LOW)  
t
WC  
VALID ADDRESS  
SCS  
ADDRESS  
CS  
t
SA  
t
t
HA  
t
AW  
t
t
PWE1  
PWE2  
WE  
t
PWB  
UB, LB  
t
HZWE  
t
LZWE  
HIGH-Z  
DATA UNDEFINED  
DOUT  
t
SD  
t
HD  
DATAIN VALID  
DIN  
Notes:  
1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CS and WE inputs and at least  
one of the LB and UB inputs being in the LOW state.  
2. WRITE = (CS) [ (LB) = (UB) ] (WE).  
Integrated Circuit Solution Inc.  
SR020-0C  
7

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