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IS62LV12816LL-100BI PDF预览

IS62LV12816LL-100BI

更新时间: 2024-01-24 11:30:24
品牌 Logo 应用领域
矽成 - ICSI 存储内存集成电路静态存储器
页数 文件大小 规格书
10页 463K
描述
128K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM

IS62LV12816LL-100BI 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:TSOP2包装说明:TSOP2-44
针数:44Reach Compliance Code:compliant
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
风险等级:5.91Is Samacsys:N
最长访问时间:100 ns其他特性:CONFIGURABLE AS 128K X 16
I/O 类型:COMMONJESD-30 代码:R-PDSO-G44
JESD-609代码:e0长度:18.41 mm
内存密度:2097152 bit内存集成电路类型:STANDARD SRAM
内存宽度:8功能数量:1
端子数量:44字数:262144 words
字数代码:256000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:256KX8输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TSOP2
封装等效代码:TSOP44,.46,32封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE并行/串行:PARALLEL
峰值回流温度(摄氏度):NOT SPECIFIED电源:3 V
认证状态:Not Qualified座面最大高度:1.2 mm
最大待机电流:0.00001 A最小待机电流:1.5 V
子类别:SRAMs最大压摆率:0.04 mA
最大供电电压 (Vsup):3.3 V最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.8 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:10.16 mm
Base Number Matches:1

IS62LV12816LL-100BI 数据手册

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IS62LV12816L  
IS62LV12816LL  
128K x 16 LOW VOLTAGE, ULTRA  
LOW POWER CMOS STATIC RAM  
FEATURES  
DESCRIPTION  
The ICSIIS62LV12816L and IS62LV12816LL are high-speed,  
2.097,152-bit static RAMs organized as 131,072 words by 16  
bits. They are fabricated using ICSI's high-performance CMOS  
technology. This highly reliable process coupled with innova-  
tive circuit design techniques, yields high-performance and  
low power consumption devices.  
• High-speed access times: 55, 70, 100 ns  
• CMOS low power operation  
-- 120 mW (typical) operating  
-- 6 µW (typical) CMOS standby  
• TTL compatible interface levels  
• Single 2.7V-3.6V Vcc power supply  
When CE is HIGH (deselected) or when CE is low and both LB  
and UB are HIGH, the device assumes a standby mode at  
which the power dissipation can be reduced by using CMOS  
input levels.  
• Fully static operation: no clock or refresh re-  
quired  
• Three state outputs  
Easy memory expansion is provided by using Chip Enable  
Output and Enable inputs, CE and OE. The active LOW Write  
Enable (WE) controls both writing and reading of the memory.  
A data byte allows Upper Byte (UB) and Lower Byte (LB)  
access.  
• Data control for upper and lower bytes  
• Industrial temperature available  
• Available in the 44-pin TSOP-2 and 48-pin  
6*8mm TF-BGA  
The IS62LV12816L and IS62LV12816LL are packaged in the  
JEDEC standare 44-pin 400mil TSOP-2 and 48-pin 6*8mm  
TF-BGA.  
FUNCTIONAL BLOCK DIAGRAM  
128K x 16  
MEMORY ARRAY  
A0-A16  
DECODER  
VCC  
GND  
I/O0-I/O7  
Lower Byte  
I/O  
DATA  
COLUMN I/O  
CIRCUIT  
I/O8-I/O15  
Upper Byte  
CE  
OE  
WE  
CONTROL  
CIRCUIT  
UB  
LB  
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors  
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.  
Integrated Circuit Solution Inc.  
SR020-0C  
1

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