Datasheet > 存储 > SRAM> IS62LV12816L-100B

IS62LV12816L-100B

更新时间： 2024-02-16 23:50:55

品牌	Logo	应用领域
矽成 - ICSI		/
页数	文件大小	规格书
10页	463K
描述
128K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM

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IS62LV12816L-100B 数据手册

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IS62LV12816L

IS62LV12816LL

IS62LV12816LL POWER SUPPLY CHARACTERISTICS⁽¹⁾(Over Operating Range)

-55

-70

-100

Symbol Parameter

Test Conditions

Min. Max.

Unit

ICC

Vcc Dynamic Operating

VCC = Max.,

Com.

Ind.

Supply Current

IOUT = 0 mA, f = fMAX

I^SB1

TTL Standby Current

(TTL Inputs)

VCC = Max.,

Com.

Ind.

0.4

1.0

0.4

1.0

0.4

1.0

VIN = VIH or VIL,

≥

VIH, f = 0

ULB Control

VCC = Max., VIN = VIH or VIL

CE VIL, f = 0, UB VIH, LB

VIH

ISB2

CMOS Standby

VCC = Max., f = 0

Com.

Ind.

µA

Current (CMOS Inputs)

VIN

≥

≤

VCC 0.2V,

VCC 0.2V, or

0.2V, f = 0

ULB Control

VCC = Max., CE

VIL

VIN

≤

0.2V, f = 0, UB / LB

VCC 0.2V

Note:

1. At f = f^MAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.

READ CYCLE SWITCHING CHARACTERISTICS⁽¹⁾(Over Operating Range)

-55

-70

-100

Min.

Symbol Parameter

Min.

Max.

Min.

Max.

Unit

tRC

Read Cycle Time

100

tAA

Address Access Time

Output Hold Time

100

tOHA

tACE

tDOE

tHZOE

CE Access Time

100

OE Access Time

(2)

OE to High-Z Output

OE to Low-Z Output

CE to High-Z Output

CE to Low-Z Output

LB, UB Access Time

LB, UB o High-Z Output

LB. UB to Low-Z Output

(2)

tLZOE

(2)

tHZCE

(2)

tLZCE

tBA

100

tHZB

tLZB

Notes:

1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.3V, input pulse levels

of 0.4V to 2.2V and output loading specified in Figure 1.

2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

Integrated Circuit Solution Inc.

SR020-0C

1 2 3 456 7 8...10

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