Datasheet > 存储 > SRAM> IS62LV12816L-100B

IS62LV12816L-100B

更新时间： 2024-02-18 08:35:48

品牌	Logo	应用领域
矽成 - ICSI		/
页数	文件大小	规格书
10页	463K
描述
128K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM

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IS62LV12816L-100B 数据手册

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IS62LV12816L

IS62LV12816LL

WRITE CYCLE SWITCHING CHARACTERISTICS^(1,2)(Over Operating Range)

-55

-70

-100

Min.

Symbol Parameter

Min.

Max.

Min.

Max.

Max

Unit

tWC

tSCE

tAW

Write Cycle Time

100

CE to Write End

Address Setup Time to Write End

Address Hold from Write End

Address Setup Time

tHA

tSA

tPWB

tPWE

tSD

LB, UB Valid to End of Write

WE Pulse Width

Data Setup to Write End

Data Hold from Write End

WE LOW to High-Z Output

WE HIGH to Low-Z Output

tHD

(3)

tHZWE

(3)

tLZWE

Notes:

1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.3V, input pulse levels of 0.4V to 2.2V

and output loading specified in Figure 1.

2. The internal write time is defined by the overlap of CE LOW, and UB or LB, and WE LOW. All signals must be in valid states to

initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the

rising or falling edge of the signal that terminates the Write.

3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

AC WAVEFORMS

WRITE CYCLE NO. 1^(1,2)(CS, Controlled, OE = HIGH or LOW)

VALID ADDRESS

SCS

ADDRESS

PWE1

PWE2

PWB

UB, LB

HZWE

LZWE

HIGH-Z

DATA UNDEFINED

DOUT

DATAIN VALID

DIN

Notes:

1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CS and WE inputs and at least

one of the LB and UB inputs being in the LOW state.

2. WRITE = (CS) [ (LB) = (UB) ] (WE).

Integrated Circuit Solution Inc.

SR020-0C

1...4 5 678 9 10

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与IS62LV12816L-100B相关器件

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IS62LV12816L-100BI	ISSI	获取价格	128K x 16 CMOS STATIC RAM
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