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IS62LV12816L-100B PDF预览

IS62LV12816L-100B

更新时间: 2024-02-18 08:35:48
品牌 Logo 应用领域
矽成 - ICSI /
页数 文件大小 规格书
10页 463K
描述
128K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM

IS62LV12816L-100B 数据手册

 浏览型号IS62LV12816L-100B的Datasheet PDF文件第4页浏览型号IS62LV12816L-100B的Datasheet PDF文件第5页浏览型号IS62LV12816L-100B的Datasheet PDF文件第6页浏览型号IS62LV12816L-100B的Datasheet PDF文件第8页浏览型号IS62LV12816L-100B的Datasheet PDF文件第9页浏览型号IS62LV12816L-100B的Datasheet PDF文件第10页 
IS62LV12816L  
IS62LV12816LL  
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)  
-55  
-70  
-100  
Min.  
Symbol Parameter  
Min.  
55  
50  
50  
0
Max.  
—
Min.  
70  
65  
65  
0
Max.  
—
Max  
—
—
—
—
—
—
—
—
—
40  
—
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tWC  
tSCE  
tAW  
Write Cycle Time  
100  
80  
80  
0
CE to Write End  
—
—
Address Setup Time to Write End  
Address Hold from Write End  
Address Setup Time  
—
—
tHA  
—
—
tSA  
0
—
0
—
0
tPWB  
tPWE  
tSD  
LB, UB Valid to End of Write  
WE Pulse Width  
45  
45  
25  
0
—
60  
60  
30  
0
—
80  
80  
40  
0
—
—
Data Setup to Write End  
Data Hold from Write End  
WE LOW to High-Z Output  
WE HIGH to Low-Z Output  
—
—
tHD  
—
—
(3)  
tHZWE  
—
5
30  
—
—
5
30  
—
—
5
(3)  
tLZWE  
Notes:  
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.3V, input pulse levels of 0.4V to 2.2V  
and output loading specified in Figure 1.  
2. The internal write time is defined by the overlap of CE LOW, and UB or LB, and WE LOW. All signals must be in valid states to  
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the  
rising or falling edge of the signal that terminates the Write.  
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.  
AC WAVEFORMS  
WRITE CYCLE NO. 1(1,2) (CS, Controlled, OE = HIGH or LOW)  
t
WC  
VALID ADDRESS  
SCS  
ADDRESS  
CS  
t
SA  
t
t
HA  
t
AW  
t
t
PWE1  
PWE2  
WE  
t
PWB  
UB, LB  
t
HZWE  
t
LZWE  
HIGH-Z  
DATA UNDEFINED  
DOUT  
t
SD  
t
HD  
DATAIN VALID  
DIN  
Notes:  
1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CS and WE inputs and at least  
one of the LB and UB inputs being in the LOW state.  
2. WRITE = (CS) [ (LB) = (UB) ] (WE).  
Integrated Circuit Solution Inc.  
SR020-0C  
7

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