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IS62LV12816L-100T PDF预览

IS62LV12816L-100T

更新时间: 2024-01-08 00:00:37
品牌 Logo 应用领域
美国芯成 - ISSI /
页数 文件大小 规格书
9页 87K
描述
128K x 16 CMOS STATIC RAM

IS62LV12816L-100T 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:TSOP2
包装说明:TSOP2-44针数:44
Reach Compliance Code:compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.91
最长访问时间:100 ns其他特性:CONFIGURABLE AS 128K X 16
I/O 类型:COMMONJESD-30 代码:R-PDSO-G44
JESD-609代码:e0长度:18.41 mm
内存密度:2097152 bit内存集成电路类型:STANDARD SRAM
内存宽度:8功能数量:1
端子数量:44字数:262144 words
字数代码:256000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:256KX8输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TSOP2
封装等效代码:TSOP44,.46,32封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE并行/串行:PARALLEL
峰值回流温度(摄氏度):240电源:3 V
认证状态:Not Qualified座面最大高度:1.2 mm
最大待机电流:0.000025 A最小待机电流:1.5 V
子类别:SRAMs最大压摆率:0.04 mA
最大供电电压 (Vsup):3.3 V最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.8 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:10.16 mm
Base Number Matches:1

IS62LV12816L-100T 数据手册

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®
ISSI  
IS62LV12816L  
128K x 16 CMOS STATIC RAM  
ADVANCE INFORMATION  
AUGUST 1998  
1
FEATURES  
DESCRIPTION  
The ISSI IS62LV12816L is a high-speed, 2,097,152-bit static  
RAM organized as 131,072 words by 16 bits. It is fabricated  
usingISSI'shigh-performanceCMOStechnology. Thishighly  
reliable process coupled with innovative circuit design  
techniques, yields high-performance and low power  
consumption devices.  
• High-speed access time: 70, 100, and 120 ns  
• CMOS low power operation  
2
– 120 mW (typical) operating  
– 6 µW (typical) CMOS standby  
• TTL compatible interface levels  
• Single 3V ± 10% VCC power supply  
3
WhenCEisHIGH(deselected),thedeviceassumesastandby  
mode at which the power dissipation can be reduced down  
with CMOS input levels.  
• Fully static operation: no clock or refresh  
required  
4
Easy memory expansion is provided by using Chip Enable  
and Output Enable inputs, CEand OE. The active LOW Write  
Enable (WE) controls both writing and reading of the memory.  
A data byte allows Upper Byte (UB) and Lower Byte (LB)  
access.  
• Three state outputs  
• Data control for upper and lower bytes  
• Industrial temperature available  
5
• Available in the 44-pin TSOP (Type II) and  
48-pin mini BGA  
The IS62LV12816L is packaged in the JEDEC standard  
44-pin TSOP (Type II) and 48-pin mini BGA.  
6
FUNCTIONAL BLOCK DIAGRAM  
7
128K x 16  
MEMORY ARRAY  
A0-A16  
DECODER  
8
VCC  
GND  
9
I/O0-I/O7  
Lower Byte  
I/O  
DATA  
COLUMN I/O  
10  
11  
12  
CIRCUIT  
I/O8-I/O15  
Upper Byte  
CE  
OE  
WE  
CONTROL  
CIRCUIT  
UB  
LB  
The specification contains ADVANCE INFORMATION. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible  
product. We assume no responsibility for any errors which may appear in this publication. © Copyright 1998, Integrated Silicon Solution, Inc.  
Integrated Silicon Solution, Inc.  
ADVANCE INFORMATION SR002-0C  
1
08/20/98  

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