Datasheet > IS62LV12816L-100BI

IS62LV12816L-100BI

更新时间： 2024-02-25 17:44:58

品牌	Logo	应用领域
美国芯成 - ISSI		/
页数	文件大小	规格书
9页	87K
描述
128K x 16 CMOS STATIC RAM

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ISSI

IS62LV12816L

ISSI

IS62LV12816L

128K x 16 CMOS STATIC RAM

ADVANCE INFORMATION

AUGUST 1998

FEATURES

DESCRIPTION

The ISSI IS62LV12816L is a high-speed, 2,097,152-bit static

RAM organized as 131,072 words by 16 bits. It is fabricated

usingISSI'shigh-performanceCMOStechnology. Thishighly

reliable process coupled with innovative circuit design

techniques, yields high-performance and low power

consumption devices.

• High-speed access time: 70, 100, and 120 ns

• CMOS low power operation

– 120 mW (typical) operating

– 6 µW (typical) CMOS standby

• TTL compatible interface levels

• Single 3V ± 10% V^CCpower supply

WhenCEisHIGH(deselected),thedeviceassumesastandby

mode at which the power dissipation can be reduced down

with CMOS input levels.

• Fully static operation: no clock or refresh

required

Easy memory expansion is provided by using Chip Enable

and Output Enable inputs, CEand OE. The active LOW Write

Enable (WE) controls both writing and reading of the memory.

A data byte allows Upper Byte (UB) and Lower Byte (LB)

access.

• Three state outputs

• Data control for upper and lower bytes

• Industrial temperature available

• Available in the 44-pin TSOP (Type II) and

48-pin mini BGA

The IS62LV12816L is packaged in the JEDEC standard

44-pin TSOP (Type II) and 48-pin mini BGA.

FUNCTIONAL BLOCK DIAGRAM

128K x 16

MEMORY ARRAY

A0-A16

DECODER

VCC

GND

I/O0-I/O7

Lower Byte

I/O

DATA

COLUMN I/O

CIRCUIT

I/O8-I/O15

Upper Byte

CONTROL

CIRCUIT

The specification contains ADVANCE INFORMATION. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible

Integrated Silicon Solution, Inc.

ADVANCE INFORMATION SR002-0C

08/20/98

12 3 4 5 6 7...9

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