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IS61WV12816DBLL-10TL-TR PDF预览

IS61WV12816DBLL-10TL-TR

更新时间: 2024-11-24 21:00:43
品牌 Logo 应用领域
美国芯成 - ISSI 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
21页 456K
描述
Application Specific SRAM, 128KX16, 10ns, CMOS, PDSO44, LEAD FREE, PLASTIC, TSOP2-44

IS61WV12816DBLL-10TL-TR 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active包装说明:TSOP2, TSOP44,.46,32
Reach Compliance Code:compliant风险等级:5.56
最长访问时间:10 nsI/O 类型:COMMON
JESD-30 代码:R-PDSO-G44JESD-609代码:e3
长度:18.415 mm内存密度:2097152 bit
内存集成电路类型:APPLICATION SPECIFIC SRAM内存宽度:16
湿度敏感等级:1功能数量:1
端子数量:44字数:131072 words
字数代码:128000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:128KX16输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TSOP2
封装等效代码:TSOP44,.46,32封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE并行/串行:PARALLEL
峰值回流温度(摄氏度):225电源:2.5/3.3 V
认证状态:Not Qualified座面最大高度:1.2 mm
最大待机电流:0.00005 A最小待机电流:2 V
子类别:SRAMs最大压摆率:0.06 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2.4 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:MATTE TIN端子形式:GULL WING
端子节距:0.8 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:10.16 mm
Base Number Matches:1

IS61WV12816DBLL-10TL-TR 数据手册

 浏览型号IS61WV12816DBLL-10TL-TR的Datasheet PDF文件第2页浏览型号IS61WV12816DBLL-10TL-TR的Datasheet PDF文件第3页浏览型号IS61WV12816DBLL-10TL-TR的Datasheet PDF文件第4页浏览型号IS61WV12816DBLL-10TL-TR的Datasheet PDF文件第5页浏览型号IS61WV12816DBLL-10TL-TR的Datasheet PDF文件第6页浏览型号IS61WV12816DBLL-10TL-TR的Datasheet PDF文件第7页 
IS61WV12816DALL/DALS  
IS61WV12816DBLL/DBLS  
IS64WV12816DBLL/DBLS  
128K x 16 HIGH SPEED ASYNCHRONOUS  
CMOS STATIC RAM  
JANUARY 2013  
DESCRIPTION  
FEATURES  
TheISSIIS61WV12816DAxx/DBxxandIS64WV12816D-  
Bxxꢀareꢀhigh-speed,ꢀ2,097,152-bitꢀstaticꢀRAMsꢀorganizedꢀ  
asꢀ131,072ꢀwordsꢀbyꢀ16ꢀbits.ꢀItꢀisꢀfabricatedꢀusingꢀISSI's  
high-performanceꢀCMOSꢀtechnology.ꢀThisꢀhighlyꢀreliableꢀ  
process coupled with innovative circuit design techniques,  
yields high-performance and low power consumption  
devices.  
HIGH SPEED: (IS61/64WV12816DALL/DBLL)  
•ꢀ High-speedꢀaccessꢀtime:ꢀ8,ꢀ10,ꢀ12,ꢀ20ꢀns  
•ꢀ LowꢀActiveꢀPower:ꢀ135ꢀmWꢀ(typical)  
•ꢀ LowꢀStandbyꢀPower:ꢀ12ꢀµWꢀ(typical)  
CMOS standby  
LOW POWER: (IS61/64WV12816DALS/DBLS)  
•ꢀ High-speedꢀaccessꢀtime:ꢀ25,ꢀ35ꢀns  
•ꢀ LowꢀActiveꢀPower:ꢀ55ꢀmWꢀ(typical)  
When CE is HIGH (deselected), the device assumes a  
standby mode at which the power dissipation can be re-  
duced down with CMOS input levels.  
•ꢀ LowꢀStandbyꢀPower:ꢀ12ꢀµWꢀ(typical)  
CMOS standby  
EasymemoryexpansionꢀisꢀprovidedꢀbyꢀusingꢀChipꢀEnableꢀ  
andꢀOutputꢀEnableꢀinputs,ꢀCEꢀandꢀOE.ꢀTheꢀactiveꢀLOWꢀ  
Write Enable (WE) controls both writing and reading of the  
memory. A data byte allows Upper Byte (UB) and Lower  
Byte (LB) access.  
•ꢀ Singleꢀpowerꢀsupply  
— Vddꢀ1.65Vꢀtoꢀ2.2Vꢀ(IS61WV12816DAxx)  
— Vddꢀ2.4Vꢀtoꢀ3.6Vꢀ(IS61/64WV12816DBxx)  
•ꢀ Fullyꢀstaticꢀoperation:ꢀnoꢀclockꢀorꢀrefreshꢀ  
Theꢀ IS61WV12816DAxx/DBxxꢀ andꢀ IS64WV12816DBxxꢀ  
areꢀꢀpackagedꢀinꢀtheꢀJEDECꢀstandardꢀ44-pinꢀTSOPꢀTypeꢀ  
IIꢀꢀandꢀ48-pinꢀMiniꢀBGAꢀ(6mmꢀxꢀ8mm).  
required  
•ꢀ Threeꢀstateꢀoutputs  
•ꢀ Dataꢀcontrolꢀforꢀupperꢀandꢀlowerꢀbytes  
•ꢀ IndustrialꢀandꢀAutomotiveꢀtemperatureꢀsupport  
•ꢀ Lead-freeꢀavailable  
FUNCTIONAL BLOCK DIAGRAM  
128K x 16  
MEMORY ARRAY  
A0-A16  
DECODER  
VDD  
GND  
I/O0-I/O7  
Lower Byte  
I/O  
DATA  
COLUMN I/O  
CIRCUIT  
I/O8-I/O15  
Upper Byte  
CE  
OE  
WE  
CONTROL  
CIRCUIT  
UB  
LB  
Copyright © 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time with-  
out notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain  
the latest version of this device specification before relying on any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. — www.issi.com  
1
Rev. E  
01/10/2013  

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