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IS61WV204816ALL-10BLI PDF预览

IS61WV204816ALL-10BLI

更新时间： 2024-11-24 20:48:43
品牌 Logo 应用领域
美国芯成 - ISSI 静态存储器内存集成电路
页数 文件大小 规格书
17页 559K
描述
Standard SRAM, 2MX16, 10ns, CMOS, PBGA48, MINIBGA-48

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IS61WV204816ALL-10BLI 技术参数

是否Rohs认证： 符合生命周期：Active
包装说明：TFBGA,Reach Compliance Code：compliant
Factory Lead Time：8 weeks风险等级：5.72
最长访问时间：10 nsJESD-30 代码：R-PBGA-B48
长度：8 mm内存密度：33554432 bit
内存集成电路类型：STANDARD SRAM内存宽度：16
功能数量：1端子数量：48
字数：2097152 words字数代码：2000000
工作模式：ASYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：2MX16
封装主体材料：PLASTIC/EPOXY封装代码：TFBGA
封装形状：RECTANGULAR封装形式：GRID ARRAY, THIN PROFILE, FINE PITCH
并行/串行：PARALLEL峰值回流温度（摄氏度）：NOT SPECIFIED
座面最大高度：1.2 mm最大供电电压 (Vsup)：2.2 V
最小供电电压 (Vsup)：1.65 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：BALL
端子节距：0.75 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：6 mm
Base Number Matches：1

IS61WV204816ALL-10BLI 数据手册

 浏览型号IS61WV204816ALL-10BLI的Datasheet PDF文件第2页浏览型号IS61WV204816ALL-10BLI的Datasheet PDF文件第3页浏览型号IS61WV204816ALL-10BLI的Datasheet PDF文件第4页浏览型号IS61WV204816ALL-10BLI的Datasheet PDF文件第5页浏览型号IS61WV204816ALL-10BLI的Datasheet PDF文件第6页浏览型号IS61WV204816ALL-10BLI的Datasheet PDF文件第7页 
IS61/64WV204816ALL  
IS61/64WV204816BLL  
OCTOBER 2016  
2Mx16 HIGH-SPEED ASYNCHRONOUS  
CMOS STATIC RAM WITH 3.3V/1.8V SUPPLY  
FEATURES  
High-speed access time: 10ns, 12ns  
High- performance, low power CMOS process  
Multiple center power and ground pins for  
greater noise immunity  
DESCRIPTION  
The ISSI IS61/64WV204816ALL/BLL are high-speed, 32M  
bit static RAMs organized as 2048K words by 16 bits. It is  
fabricated using ISSI's high-performance CMOS technology.  
Easy memory expansion with CS# and OE#  
TTL compatible inputs and outputs  
Single power supply  
This highly reliable process coupled with innovative circuit  
design techniques, yields high-performance and low power  
consumption devices.  
–
–
1.65V-2.2V VDD (IS61/64WV204816ALL)  
2.4V-3.6V VDD (IS61/64WV204816BLL)  
When CS# is HIGH (deselected), the device assumes a  
standby mode at which the power dissipation can be  
reduced down with CMOS input levels. Easy memory  
expansion is provided by using Chip Enable and Output  
Enable inputs. The active LOW Write Enable (WE#)  
controls both writing and reading of the memory. A data  
byte allows Upper Byte (UB#) and Lower Byte (LB#) access.  
Packages available :  
- 48 ball mini BGA (6mm x 8mm)  
- 48 pin TSOP (Type I)  
Industrial and Automotive temperature support  
Lead-free available  
The device is packaged in the JEDEC standard 48-Pin  
TSOP (TYPE I) and 48-pin mini BGA (6mm x 8mm).  
Data Control for upper and lower bytes  
FUNCTIONAL BLOCK DIAGRAM  
2048K x16  
MEMORY  
ARRAY  
DECODER  
A0 – A20  
VDD  
VSS  
I/O0– I/O7  
Lower Byte  
I/ O  
DATA  
COLUMN IO  
I/O8– I/O15  
CIRCUIT  
Upper Byte  
CS#  
CONTROL  
CIRCUIT  
OE#  
WE#  
UB#  
LB#  
Copyright © 2016 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time  
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to  
obtain the latest version of this device specification before relying on any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can  
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such  
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:  
a.) the risk of injury or damage has been minimized;  
b.) the user assume all such risks; and  
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances  
Integrated Silicon Solution, Inc.- www.issi.com  
1
Rev. A  
10/27/2016  
1234567...17

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