Datasheet > IS61VPD51218A-250TQI

IS61VPD51218A-250TQI

更新时间： 2024-11-27 04:44:47

品牌	Logo	应用领域
美国芯成 - ISSI		/
页数	文件大小	规格书
32页	208K
描述
256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM

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IS61VPD25636A IS61LPD25636A

IS61VPD51218A IS61LPD51218A

ISSI

256K x 36, 512K x 18

9 Mb SYNCHRONOUS PIPELINED,

DOUBLE CYCLE DESELECT STATIC RAM

MAY 2005

DESCRIPTION

FEATURES

The ISSIIS61LPD/VPD25636AandIS61LPD/VPD51218A

are high-speed, low-power synchronous static RAMs de-

signed to provide burstable, high-performance memory for

communicationandnetworkingapplications.TheIS61LPD/

VPD25636Aisorganizedas262,144wordsby36bits,and

the IS61LPD/VPD51218A is organized as 524,288 words

by18bits.FabricatedwithISSI'sadvancedCMOStechnol-

ogy,thedeviceintegratesa2-bitburstcounter,high-speed

SRAM core, and high-drive capability outputs into a single

monolithic circuit. All synchronous inputs pass through

registers controlled by a positive-edge-triggered single

clock input.

• Internal self-timed write cycle

• Individual Byte Write Control and Global Write

• Clock controlled, registered address, data and

control

• Burst sequence control using MODE input

• Three chip enable option for simple depth

expansion and address pipelining

• Common data inputs and data outputs

• Auto Power-down during deselect

• Double cycle deselect

Writecyclesareinternallyself-timedandareinitiatedbythe

risingedgeoftheclockinput.Writecyclescanbeonetofour

bytes wide as controlled by the write control inputs.

• Snooze MODE for reduced-power standby

• JTAG Boundary Scan for PBGA package

• Power Supply

Separate byte enables allow individual bytes to be written.

The byte write operation is performed by using the byte

write enable (BWE) input combined with one or more

individual byte write signals (BWx). In addition, Global

Write (GW) is available for writing all bytes at one time,

regardless of the byte write controls.

LPD: V^DD3.3V + 5%, VDDQ 3.3V/2.5V + 5%

VPD: V^DD2.5V + 5%, VDDQ 2.5V + 5%

Bursts can be initiated with either ADSP (Address Status

Processor) or ADSC (Address Status Cache Controller)

input pins. Subsequent burst addresses can be generated

internally and controlled by the ADV (burst address

advance) input pin.

• JEDEC 100-Pin TQFP,

119-pin PBGA and 165-pin PBGA package

The mode pin is used to select the burst sequence order,

Linear burst is achieved when this pin is tied LOW.

Interleave burst is achieved when this pin is tied HIGH or

left floating.

FAST ACCESS TIME

Symbol

tKQ

Parameter

250

2.6

200

3.1

Units

Clock Access Time

Cycle Time

tKC

Frequency

250

200

MHz

Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability

arisingoutoftheapplicationoruseofanyinformation, productsorservicesdescribedherein. Customersareadvisedtoobtainthelatestversionofthisdevicespecificationbeforerelyingonany

publishedinformationandbeforeplacingordersforproducts.

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

05/09/05

12 3 4 5 6 7...32

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与IS61VPD51218A-250TQI相关器件

型号	品牌	获取价格	描述	数据表
IS61VPD51236-200B3	ISSI	获取价格	Cache SRAM, 512KX36, 3.1ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, PLASTIC, BGA-165
IS61VPD51236-200TQ	ISSI	获取价格	Cache SRAM, 512KX36, 3.1ns, CMOS, PQFP100, TQFP-100
IS61VPD51236-200TQI	ISSI	获取价格	Cache SRAM, 512KX36, 3.1ns, CMOS, PQFP100, TQFP-100
IS61VPD51236-250B2I	ISSI	获取价格	Cache SRAM, 512KX36, 2.6ns, CMOS, PBGA119, 14 X 22 MM, 1 MM PITCH, PLASTIC, BGA-119
IS61VPD51236-250B3	ISSI	获取价格	Cache SRAM, 512KX36, 2.6ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, PLASTIC, BGA-165
IS61VPD51236-250B3I	ISSI	获取价格	Cache SRAM, 512KX36, 2.6ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, PLASTIC, BGA-165
IS61VPD51236A	ISSI	获取价格	512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM
IS61VPD51236A-200B3	ISSI	获取价格	512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM
IS61VPD51236A-200B3I	ISSI	获取价格	512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM
IS61VPD51236A-200TQ	ISSI	获取价格	512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM

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